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    Field effect transistor and method of forming a field effect transistor
    11.
    发明授权
    Field effect transistor and method of forming a field effect transistor 有权
    场效应晶体管和形成场效应晶体管的方法

    公开(公告)号：US07629211B2

    公开(公告)日：2009-12-08

    申请号：US11684211

    申请日：2007-03-09

    申请人： Sven Beyer ,  Thorsten Kammler ,  Rolf Stephan ,  Manfred Horstmann

    发明人： Sven Beyer ,  Thorsten Kammler ,  Rolf Stephan ,  Manfred Horstmann

    IPC分类号： H01L21/331 ,  H01L21/8234

    CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

    摘要： A method of forming a field effect transistor comprises providing a semiconductor substrate, a gate electrode being formed over the semiconductor substrate. At least one cavity is formed adjacent the gate electrode. A strain-creating element is formed in the at least one cavity. The strain-creating element comprises a compound material comprising a first chemical element and a second chemical element. A first concentration ratio between a concentration of the first chemical element in a first portion of the strain-creating element and a concentration of the second chemical element in the first portion of the strain-creating element is different from a second concentration ratio between a concentration of the first chemical element in a second portion of the strain-creating element and a concentration of the second chemical element in the second strain-creating element.

    摘要翻译： 形成场效应晶体管的方法包括提供半导体衬底，栅电极形成在半导体衬底上。 在栅电极附近形成至少一个空腔。 应变产生元件形成在至少一个空腔中。 应变产生元件包括包含第一化学元素和第二化学元素的复合材料。 应变产生元件的第一部分中的第一化学元素的浓度与应变产生元件的第一部分中的第二化学元素的浓度之间的第一浓度比不同于第二浓度比， 的应变产生元件的第二部分中的第一化学元素和第二应变产生元件中的第二化学元素的浓度。

    ENHANCING TRANSISTOR CHARACTERISTICS BY A LATE DEEP IMPLANTATION IN COMBINATION WITH A DIFFUSION-FREE ANNEAL PROCESS
    12.
    发明申请
    ENHANCING TRANSISTOR CHARACTERISTICS BY A LATE DEEP IMPLANTATION IN COMBINATION WITH A DIFFUSION-FREE ANNEAL PROCESS 有权
    通过最后深度植入与无扩张的方法进行组合来增强晶体管特性

    公开(公告)号：US20080268625A1

    公开(公告)日：2008-10-30

    申请号：US12023743

    申请日：2008-01-31

    申请人： Thomas Feudel ,  Rolf Stephan ,  Manfred Horstmann

    发明人： Thomas Feudel ,  Rolf Stephan ,  Manfred Horstmann

    IPC分类号： H01L21/425

    CPC分类号： H01L21/26513 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/84 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7848

    摘要： By combining an anneal process for adjusting the effective channel length and a substantially diffusion-free anneal process performed after a deep drain and source implantation, the vertical extension of the drain and source region may be increased substantially without affecting the previously adjusted channel length. In this manner, in SOI devices, the drain and source regions may extend down to the buried insulating layer, thereby reducing the parasitic capacitance, while the degree of dopant activation and thus series resistance in the extension regions may be improved. Furthermore, less critical process parameters during the anneal process for adjusting the channel length may provide the potential for reducing the lateral dimensions of the transistor devices.

    摘要翻译： 通过组合用于调节有效沟道长度的退火工艺和在深漏极和源极注入之后执行的基本上无扩散的退火工艺，可以基本上增加漏极和源极区域的垂直延伸，而不影响先前调节的沟道长度。 以这种方式，在SOI器件中，漏极和源极区域可以向下延伸到掩埋绝缘层，从而减小寄生电容，同时可以改善延伸区域中的掺杂剂激活程度和因此的串联电阻。 此外，在用于调整沟道长度的退火工艺期间较不重要的工艺参数可以为降低晶体管器件的横向尺寸提供潜力。

    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE
    13.
    发明申请
    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE 有权
    形成半导体结构的方法

    公开(公告)号：US20080242040A1

    公开(公告)日：2008-10-02

    申请号：US11942400

    申请日：2007-11-19

    申请人： Frank Wirbeleit ,  Rolf Stephan ,  Manfred Horstmann

    发明人： Frank Wirbeleit ,  Rolf Stephan ,  Manfred Horstmann

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28123 ,  H01L29/66545 ,  H01L29/6659

    摘要： A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate.

    摘要翻译： 形成半导体结构的方法包括提供半导体衬底。 在衬底上形成特征。 该特征在横向上基本上是均匀的。 执行适于将第一掺杂剂离子引入邻近该特征的衬底的至少一部分中的第一离子注入工艺。 横向的特征长度减小。 在特征的长度减小之后，执行适于将第二掺杂剂离子引入邻近该特征的衬底的至少一部分中的第二离子注入工艺。 该特征可以是要形成在半导体衬底上的场效应晶体管的栅电极。

    Method of forming different silicide portions on different silicon-containing regions in a semiconductor device
    15.
    发明授权
    Method of forming different silicide portions on different silicon-containing regions in a semiconductor device 有权
    在半导体器件中在不同含硅区域上形成不同硅化物部分的方法

    公开(公告)号：US07226859B2

    公开(公告)日：2007-06-05

    申请号：US10282720

    申请日：2002-10-29

    申请人： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

    发明人： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

    IPC分类号： H01L29/40

    CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/4933

    摘要： A method is disclosed in which differing metal layers are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a heat treatment is performed to convert the metals into metal silicides so as to improve the electrical conductivity of the silicon-containing regions. In this way, silicide portions may be formed that are individually adapted to specific silicon-containing regions so that device performance of individual semiconductor elements or the overall performance of a plurality of semiconductor elements may significantly be improved. Moreover, a semiconductor device is disclosed comprising at least two silicon-containing regions having formed therein differing silicide portions, wherein at least one silicide portion comprises a noble metal.

    摘要翻译： 公开了一种方法，其中不同的金属层依次沉积在含硅区域上，使得金属层的类型和厚度可以适应于下面的含硅区域的特定特性。 随后，进行热处理以将金属转化为金属硅化物，从而提高含硅区域的导电性。 以这种方式，可以形成独立地适应特定的含硅区域的硅化物部分，从而可以显着提高单个半导体元件的器件性能或多个半导体元件的整体性能。 此外，公开了一种半导体器件，其包括至少两个其中形成有不同硅化物部分的含硅区域，其中至少一个硅化物部分包括贵金属。

    Field effect transistor with reduced gate delay and method of fabricating the same
    16.
    发明授权
    Field effect transistor with reduced gate delay and method of fabricating the same 有权
    具有减小的栅极延迟的场效应晶体管及其制造方法

    公开(公告)号：US06798028B2

    公开(公告)日：2004-09-28

    申请号：US09847622

    申请日：2001-05-02

    申请人： Manfred Horstmann ,  Rolf Stephan ,  Karsten Wieczorek ,  Stephan Kruegel

    发明人： Manfred Horstmann ,  Rolf Stephan ,  Karsten Wieczorek ,  Stephan Kruegel

    IPC分类号： H01L2976

    CPC分类号： H01L21/28052 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4933

    摘要： A transistor formed on a substrate comprises a gate electrode having a lateral extension at the foot of the gate electrode that is less than the average lateral extension of the gate electrode. The increased cross-section of the gate electrode compared to the rectangular cross-sectional shape of a prior art device provides for a significantly reduced gate resistance while the effective gate length, i.e., the lateral extension of the gate electrode at its foot, may be scaled down to a size of 100 nm and beyond. Moreover, a method for forming the field effect transistor described above is disclosed.

    摘要翻译： 形成在基板上的晶体管包括栅电极，栅电极在栅极的脚处具有小于栅电极的平均横向延伸的横向延伸。 与现有技术的器件的矩形横截面形状相比，栅电极的横截面增加提供了显着降低的栅极电阻，而有效栅极长度，即栅电极在其脚处的横向延伸可以是 缩小到100nm以上的尺寸。 此外，公开了一种用于形成上述场效应晶体管的方法。