公开(公告)号：US20240204066A1

公开(公告)日：2024-06-20

申请号：US18543315

申请日：2023-12-18

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Julien Jussot

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10B10/00

CPC classification number: H01L29/41758 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78696 ,  H10B10/12

Abstract: The disclosure relates to a semiconductor device structure. The device structure comprises a first and second FETs, each comprising respective S/D structures, a respective channel structure and a respective gate structure. Each S/D structure comprises an S/D body and a set of vertically spaced apart S/D prongs protruding laterally from the S/D body. The S/D prongs of the first and second FETs extend in opposite lateral directions. Each gate structure comprises a gate body and a set of gate prongs protruding laterally from the gate body into spaces between channel layers of the respective channel structures. The gate prongs of the first and second FETs extend in opposite lateral directions.

公开(公告)号：US11765910B2

公开(公告)日：2023-09-19

申请号：US17092135

申请日：2020-11-06

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Shamin Houshmand Sharifi ,  Luka Kljucar

IPC: H10B61/00 ,  H01L29/872 ,  G11C11/16 ,  H01L29/221 ,  H01L29/66 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/10 ,  G11C11/161 ,  H01L29/221 ,  H01L29/66143 ,  H01L29/872 ,  H10N50/01 ,  H10N50/80

Abstract: The disclosed technology relates to a selector device for a memory array, and a method of forming the selector device. In some embodiments, the selector device comprises a first electrode layer embedded in an oxide; a second electrode layer arranged above the first electrode layer and separated from the first electrode layer by the oxide; and a semiconductor material forming a semiconductor layer on the top surface of the second electrode layer, and extending through the second electrode layer and the oxide onto the top surface of the first electrode layer, wherein the semiconductor material contacts the first electrode layer and the second electrode layer. In some embodiments, the selector device helps to solve the sneak path problem in the memory array it is inserted into.

公开(公告)号：US11257764B2

公开(公告)日：2022-02-22

申请号：US16874446

申请日：2020-05-14

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Geert Van Der Plas

IPC: H01L23/538 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/50 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit (IC) chip that includes a semiconductor substrate including active devices on its front side, and at least part of a power delivery network (PDN) on its back side, is disclosed. In one aspect, the PDN includes a power supply terminal (Vdd) and a reference terminal (Vss) at the back of the IC. A plurality of TSV (Through Semiconductor Via) connections through the substrate bring the power to the front of the substrate. A field effect transistor is integrated at the back side of the substrate, and includes a source electrode, a drain electrode, and a gate electrode, which are contacted at the back side of the substrate. The IC further includes a gate control terminal for controlling the gate voltage. The transistor is coupled between the power supply terminal and one or more of the active devices of the IC.

公开(公告)号：US11038067B2

公开(公告)日：2021-06-15

申请号：US16676882

申请日：2019-11-07

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Luka Kljucar

IPC: H01L29/84 ,  G01L1/20 ,  H01L23/528 ,  H01L29/417 ,  H01L29/43 ,  H01L29/45

Abstract: A sensor for measuring mechanical stress in a layered metallization structure such as the back end of line portion of an integrated circuit die is provided. The sensor operates as a field effect transistor comprising a gate electrode, gate dielectric, channel and source and drain electrodes, wherein the gate electrode is a conductor of a first metallization level and the source and drain electrodes are two interconnect vias, connecting the channel to respective conductors in an adjacent level. At least one of the interconnect vias is formed of a material whereof the electrical resistance is sensitive to mechanical stress in the direction of the via. The sensitivity of the electrical resistance to the mechanical stress is sufficient to facilitate measurement of the stress by reading out the drain current of the transistor. The sensor thereby allows monitoring of stress in the BEOL prior to cracking.

公开(公告)号：US20210143213A1

公开(公告)日：2021-05-13

申请号：US17092135

申请日：2020-11-06

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Shamin Houshmand Sharifi ,  Luka Kljucar

IPC: H01L27/22 ,  G11C11/16 ,  H01L29/872 ,  H01L29/221 ,  H01L29/66 ,  H01L43/02 ,  H01L43/12

Abstract: The disclosed technology relates to a selector device for a memory array, and a method of forming the selector device. In some embodiments, the selector device comprises a first electrode layer embedded in an oxide; a second electrode layer arranged above the first electrode layer and separated from the first electrode layer by the oxide; and a semiconductor material forming a semiconductor layer on the top surface of the second electrode layer, and extending through the second electrode layer and the oxide onto the top surface of the first electrode layer, wherein the semiconductor material contacts the first electrode layer and the second electrode layer. In some embodiments, the selector device helps to solve the sneak path problem in the memory array it is inserted into.

公开(公告)号：US20210134995A1

公开(公告)日：2021-05-06

申请号：US17090758

申请日：2020-11-05

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Sylvain Baudot

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78

Abstract: The disclosed technology relates generally to semiconductor devices, and more particularly to a vertical channel device and a method of forming a vertical channel device. In one aspect, a method of forming a vertical channel transistor structure comprises the steps of: (a) forming a bottom source/drain region on a substrate surface and depositing a spacer oxide layer over the bottom source/drain region; (b) forming vertically extending portions and depositing a gate material on the deposited spacer oxide layer such that the gate material is arranged over the bottom source/drain region and over the deposited spacer oxide layer, wherein the vertically extending portions are arranged around and extend above the gate material; and (c) depositing a spacer material at sidewalls of the vertically extending portions, thereby defining a horizontal gap between the vertically extending portions, the gap being positioned vertically over the gate material and the bottom source/drain portion. The method further comprises the steps of: (d) forming a vertical opening through the gate material extending from the horizontal gap down to the bottom source/drain region; (e) depositing an oxide at sidewalls of the gate material in the vertical opening; (f) performing an epitaxial deposition process of a semiconductor material on the bottom source/drain portion to form a vertical channel structure above the gate material, wherein a width (w1) of the vertical channel structure through the gate is defined by a width of the horizontal gap after depositing the oxide in step (e); (g) planarizing the vertical channel transistor structure, thereby reducing the height of the vertical channel structure and the spacer material; and (h) forming a top source/drain region over the vertical channel structure.

公开(公告)号：US10811315B2

公开(公告)日：2020-10-20

申请号：US16456833

申请日：2019-06-28

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Stefaan Van Huylenbroeck ,  Geert Van der Plas

IPC: H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L25/065 ,  H01L23/538 ,  H01L23/48 ,  H01L23/00

Abstract: A method of producing a through semiconductor via (TSV) connection is disclosed. In one aspect, an opening of the TSV is produced for contacting a first semiconductor die bonded to a second die or to a temporary carrier. The first die includes fin-shaped devices in the front end of line of the die. Etching of the TSV opening does not end on a metal pad, but the opening is etched until reaching a well that is formed of material of a first doping type and formed in the first die amid semiconductor material of a second doping type opposite the first. After filling the TSV opening with a conductive material, the TSV connects to a conductor of an intermediate metallization (IM) of the first die through at least one fin extending from the well and connected to the conductor. A package of dies comprising at least one TSV produced by the above method is also disclosed.

公开(公告)号：US20230121515A1

公开(公告)日：2023-04-20

申请号：US18047060

申请日：2022-10-17

Applicant: IMEC VZW

Inventor： Gaspard Hiblot

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L29/417

Abstract: A method for forming an interconnection structure for a first transistor and a second transistor is provided, wherein the first transistor includes a horizontally extending first channel portion (112) and the second transistor includes a horizontally extending second (122) channel portion, and wherein the channel portions are stacked above each other on a substrate. The method comprises forming a conductive line (130) extending beside and below the second channel portion, forming, on the conductive line, a first vertical interconnect structure (132) for electrically contacting the first channel portion, and thinning the substrate from the backside to expose the conductive line from below. The method further comprises forming a via hole (146) exposing the second channel portion from below, filling the via hole with a conductive material to form a second vertical interconnect structure (142), and forming a conductive structure (140) on the second vertical interconnect structure. A semiconductor device is also provided.

公开(公告)号：US11621295B2

公开(公告)日：2023-04-04

申请号：US17092130

申请日：2020-11-06

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Shamin Houshmand Sharifi ,  Geert Van der Plas

IPC: H01L27/22 ,  G11C5/06 ,  G11C11/16 ,  H01L43/02 ,  H01L43/12

Abstract: The disclosed technology relates to the field of memory devices including memory arrays, and more particularly, to magnetic memory devices. In one aspect, the disclosed technology provides a method of fabricating a memory device, and the memory device. The method comprises: processing a plurality of selector devices in a semiconductor layer of a first substrate, processing an interconnect layer on a front-side of the semiconductor layer, the interconnect layer comprising an interconnect structure electrically connected to the plurality of selector devices, processing a plurality of memory elements in an oxide layer of the first substrate arranged on a back-side of the semiconductor layer, each memory element being electrically connected to one of the selector devices, and processing one or more vias through the semiconductor layer to electrically connect the memory elements to the interconnect structure.

公开(公告)号：US20230025767A1

公开(公告)日：2023-01-26

申请号：US17869289

申请日：2022-07-20

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Geert Hellings ,  Geert Van der Plas

IPC: H01L23/528 ,  H01L29/66 ,  H01L29/786

Abstract: An example includes a semiconductor structure including a semiconductor layer, front-side logic devices arranged in a front-side of the semiconductor layer, four epitaxial layers on a back-side of the semiconductor layer, where the four epitaxial layers include a first epitaxial layer of a first conductivity type, a second epitaxial layer of a second conductivity type, a third epitaxial layer of the second conductivity type, and a fourth epitaxial layer of the first conductivity type, a plurality of back-side contacts exposed at a back-side surface of the fourth epitaxial layer, where the plurality of back-side contacts include a set of first terminal contacts extending into and contacting the fourth epitaxial layer, a set of second terminal contacts extending into and contacting the second epitaxial layer, a set of first gate contacts extending into the third epitaxial layer, and a set of second gate contacts extending into the first epitaxial layer.