公开(公告)号：US11423983B2

公开(公告)日：2022-08-23

申请号：US17322509

申请日：2021-05-17

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Chih-Sheng Lin ,  Sih-Han Li ,  Yu-Hui Lin ,  Jian-Wei Su

IPC: G11C11/00 ,  G11C13/00 ,  G11C7/06

Abstract: A memory device for in-memory computation includes data channels, a memory cell array, a maximum accumulated weight generating array, a minimum accumulated weight generating array, a reference generator and a comparator. The data channels are selectively enabled according to data input. The memory cell array generates an accumulated data weight value according to the quantity of enabled data channels, a first resistance and a second resistance. The maximum accumulated weight generating array generates a maximum accumulated weight value according to the quantity of enabled data channels and the first resistance. The minimum accumulated weight generating array generates a minimum accumulated weight value according to the quantity of enabled data channels and the second resistance. The reference generator generates reference value(s) according to the maximum and minimum accumulated weight values. The comparator compares the accumulated data weight value with the reference value(s) to generate a data weight state.

公开(公告)号：US20210192327A1

公开(公告)日：2021-06-24

申请号：US17131783

申请日：2020-12-23

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Shih-Chieh Chang ,  Shyh-Shyuan Sheu ,  Jian-Wei Su ,  Fu-Cheng Tsai

IPC: G06N3/063 ,  G06N3/04

Abstract: An apparatus and a method for neural network computation are provided. The apparatus for neural network computation includes a first neuron circuit and a second neuron circuit. The first neuron circuit is configured to execute a neural network computation of at least one computing layer with a fixed feature pattern in a neural network algorithm. The second neuron circuit is configured to execute the neural network computation of at least one computing layer with an unfixed feature pattern in the neural network algorithm. The performance of the first neuron circuit is greater than that of the second neuron circuit.

公开(公告)号：US10156535B2

公开(公告)日：2018-12-18

申请号：US14961906

申请日：2015-12-08

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Chih-Sheng Lin ,  Kuan-Wei Chen ,  Erh-Hao Chen ,  Shyh-Shyuan Sheu

IPC: G01N27/12

Abstract: A sensor device and a method of manufacturing the same are provided. The sensor device includes a substrate, a plurality of sensing electrodes, a humidity nanowire sensor, a temperature nanowire sensor, and a gas nanowire sensor. The sensing electrodes are formed on the substrate, and the humidity, the temperature and the gas nanowire sensors are also on the substrate. The humidity nanowire sensor includes an exposed first nanowire sensing region, the temperature nanowire sensor includes a second nanowire sensing region, and the gas nanowire sensor includes a third nanowire sensing region.

公开(公告)号：US20170115248A1

公开(公告)日：2017-04-27

申请号：US14958856

申请日：2015-12-03

Applicant: Industrial Technology Research Institute

Inventor： Chih-Sheng Lin ,  Erh-Hao Chen ,  Sih-Han Li ,  Kuan-Wei Chen ,  Shyh-Shyuan Sheu

IPC: G01N27/12

CPC classification number: G01N27/127

Abstract: A gas sensing apparatus including a gas sensor, a gas determining circuit and a gas database is provided. The gas sensor includes at least two nanowire sensors. The gas sensor is configured to sense multiple gases and output a plurality of sensing signals. The gas determining circuit is coupled to the gas sensor. The gas determining circuit is configured to receive the sensing signals and determine types of the gases according to reference data and the sensing signals. The gas database is coupled to the gas determining circuit. The gas database stores the reference data and outputs the reference data to the gas determining circuit. Each of the nanowire sensors includes at least one nanowire. Structural properties of the nanowires are different.

公开(公告)号：US20140175606A1

公开(公告)日：2014-06-26

申请号：US13974909

申请日：2013-08-23

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Sih-Han Li ,  Pei-Ling Tseng ,  Zhe-Hui Lin ,  Chih-Sheng Lin

IPC: H01L49/02

CPC classification number: H01L23/481 ,  H01L27/0808 ,  H01L29/93 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A varactor is provided. A substrate includes a first surface, a second surface and a first opening and a second opening in the substrate. A conductive material is filling the first and second openings, to form a first through-wafer via (TWV) and a second through-wafer via. A first capacitor is coupled between the first through-wafer via and a first terminal. A second capacitor is coupled between the second through-wafer via and a second terminal. A capacitance of a depletion-region capacitor between the first through-wafer via and the second through-wafer via is determined by a bias voltage applied to the first through-wafer via and the second through-wafer via.

Abstract translation: 提供变容二极管。 衬底包括衬底中的第一表面，第二表面和第一开口以及第二开口。 导电材料填充第一和第二开口，以形成第一贯穿晶片通孔（TWV）和第二通晶片通孔。 第一电容器耦合在第一通晶片通孔和第一端子之间。 第二电容器耦合在第二通晶片通孔和第二端子之间。 第一贯穿晶片通孔和第二贯通晶片通孔之间的耗尽区电容器的电容由施加到第一贯穿晶片通孔和第二贯通晶片通孔的偏置电压决定。

公开(公告)号：US20140115243A1

公开(公告)日：2014-04-24

申请号：US13974001

申请日：2013-08-22

Applicant: Industrial Technology Research Institute

Inventor： Chih-He Lin ,  Sih-Han Li ,  Wen-Pin Lin ,  Shyh-Shyuan Sheu

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0054 ,  G11C2013/0076

Abstract: A resistive random-access memory device includes a memory array, a read circuit, a write-back logic circuit and a write-back circuit. The read circuit reads the data stored in a selected memory cell and accordingly generates a first control signal. The write-back logic circuit generates a write-back control signal according to the first control signal and a second control signal. The write-back circuit performs a write-back operation on the selected memory cell according to the write-back control signal and a write-back voltage, so as to change a resistance state of the selected memory cell from a low resistance state to a high resistance state, and generates the second control signal according to the resistance state of the selected memory cell.

Abstract translation: 电阻式随机存取存储器件包括存储器阵列，读取电路，回写逻辑电路和回写电路。 读取电路读取存储在所选择的存储器单元中的数据，并且相应地产生第一控制信号。 回写逻辑电路根据第一控制信号和第二控制信号产生回写控制信号。 回写电路根据回写控制信号和回写电压对所选择的存储单元执行写回操作，以将所选存储单元的电阻状态从低电阻状态改变为 并且根据所选存储单元的电阻状态产生第二控制信号。

公开(公告)号：US12265904B2

公开(公告)日：2025-04-01

申请号：US17131783

申请日：2020-12-23

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Shih-Chieh Chang ,  Shyh-Shyuan Sheu ,  Jian-Wei Su ,  Fu-Cheng Tsai

IPC: G06N3/063 ,  G06N3/045 ,  G06N3/0455

Abstract: An apparatus and a method for neural network computation are provided. The apparatus for neural network computation includes a first neuron circuit and a second neuron circuit. The first neuron circuit is configured to execute a neural network computation of at least one computing layer with a fixed feature pattern in a neural network algorithm. The second neuron circuit is configured to execute the neural network computation of at least one computing layer with an unfixed feature pattern in the neural network algorithm. The performance of the first neuron circuit is greater than that of the second neuron circuit.

公开(公告)号：US12231086B2

公开(公告)日：2025-02-18

申请号：US18097933

申请日：2023-01-17

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Jie Zhang ,  Sih-Han Li

IPC: H03D7/14

Abstract: A switching circuit includes a transmission gate, two base control sub-circuits each including a first transistor and a second transistor, a third transistor, and a fourth transistor. The transmission gate includes two I/O terminals, two gate control terminals, and two base control terminals, and is configured to conduct or not conduct the two I/O terminals according to the voltage of the two gate control terminals. The two base voltage control sub-circuits, the third transistor and the fourth transistor forms a double balance circuit structure and is electrically connected to the transmission gate. The double balance circuit changes the voltage of the base control terminals according to the voltage of the I/O terminals of the transmission gate.

公开(公告)号：US12163989B2

公开(公告)日：2024-12-10

申请号：US17559371

申请日：2021-12-22

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Sih-Han Li ,  Jie Zhang ,  Peng-I Mei

IPC: G01R27/32 ,  G01R35/00

Abstract: A high-frequency component test device including a test key and a test module is provided. The test key includes a front-level key and a back-level key which are arranged symmetrically and have the same electrical length and characteristic impedance. The test module is used to measure an S parameter of the front-level key and the back-level key connected directly and an S parameter of a structure where a device under test (DUT) is added between the front-level key and the back-level key. The test module performs S parameter calculation in the frequency domain and converts the S parameter into an ABCD parameter matrix, and then obtains an ABCD parameter of a de-embedded DUT using a matrix root-opening operation and an inverse matrix operation.

公开(公告)号：US12154905B2

公开(公告)日：2024-11-26

申请号：US17372132

申请日：2021-07-09

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Jie Zhang ,  Tai-Hsing Lee ,  Sih-Han Li

IPC: H01L27/118 ,  H01L25/065 ,  H03K17/60 ,  H03K17/687 ,  H01L23/00

Abstract: An arrayed switch circuit includes a substrate, signal conductive pads and signal expansion pins. The signal conductive pads are disposed on the substrate at intervals, and the signal conductive pads are arranged to form a signal conductive pad array. Each of the signal conductive pads has a row position and a column position in the signal conductive pad array. A row signal switch is provided between any two adjacent signal conductive pads corresponding to the same row position, and a column signal switch is provided between any two adjacent signal conductive pads corresponding to the same column position. The signal expansion pins are connected to the signal conductive pads located on at least one side of the signal conductive pad array through signal expansion switches respectively.