公开(公告)号：US11063142B2

公开(公告)日：2021-07-13

申请号：US16721088

申请日：2019-12-19

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Wolfgang Bergner ,  Christian Hecht ,  Hans-Joachim Schulze ,  Andre Rainer Stegner

IPC: H01L29/739 ,  H01L29/16 ,  H01L29/32 ,  H01L29/40 ,  H01L29/66 ,  H01L21/04 ,  H01L29/47

Abstract: A semiconductor device includes a silicon carbide body that includes a first section and a second section. The first section is adjacent to the second section. A drift region is formed in the first section and the second section. A lattice defect region is in a portion of the drift region in the second section. A first density of lattice defects, which include interstitials and vacancies in the lattice defect region, is at least double a second density of lattice defects, which include interstitials and vacancies in a portion of the drift region outside the lattice defect region.

公开(公告)号：US20160104779A1

公开(公告)日：2016-04-14

申请号：US14974553

申请日：2015-12-18

Applicant: Infineon Technologies AG

Inventor： Roland Rupp ,  Christian Hecht ,  Jens Konrath ,  Wolfgang Bergner ,  Hans-Joachim Schulze ,  Rudolf Elpelt

IPC: H01L29/16 ,  H01L21/04 ,  H01L29/06 ,  H01L21/56 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L29/1608 ,  H01L21/045 ,  H01L21/046 ,  H01L21/047 ,  H01L21/0495 ,  H01L21/565 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/3171 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7811 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A silicon carbide device includes a silicon carbide substrate, an inorganic passivation layer structure and a molding material layer. The inorganic passivation layer structure laterally covers at least partly a main surface of the silicon carbide substrate and the molding material layer is arranged adjacent to the inorganic passivation layer structure.

Abstract translation: 碳化硅器件包括碳化硅衬底，无机钝化层结构和成型材料层。 无机钝化层结构至少部分地覆盖碳化硅衬底的主表面，并且模制材料层被布置成与无机钝化层结构相邻。

公开(公告)号：US20150008447A1

公开(公告)日：2015-01-08

申请号：US13933686

申请日：2013-07-02

Applicant: Infineon Technologies AG

Inventor： Roland Rupp ,  Christian Hecht ,  Bernd Leonhard Zippelius

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/02

CPC classification number: H01L29/0607 ,  H01L29/1608 ,  H01L29/32 ,  H01L29/34 ,  H01L29/66068 ,  H01L29/7827

Abstract: A silicon carbide device includes an epitaxial silicon carbide layer having a first conductivity type and a buried lateral silicon carbide edge termination region within the epitaxial silicon carbide layer and having a second conductivity type. The buried lateral silicon carbide edge termination region is covered by a silicon carbide surface layer including a doping of ions of a transition metal or including an increased density of intrinsic point defects in comparison to a density of intrinsic point defects of the buried lateral silicon carbide edge termination region.

Abstract translation: 碳化硅器件包括在外延碳化硅层内具有第一导电类型和掩埋侧向碳化硅边缘终止区的外延碳化硅层并且具有第二导电类型。 掩埋的横向碳化硅边缘终止区域被碳化硅表面层覆盖，该碳化硅表面层包括掺杂过渡金属的离子，或者与埋入的侧向碳化硅边缘的固有点缺陷的密度相比包括增加的本征点缺陷密度 终止区域。

公开(公告)号：US20140264374A1

公开(公告)日：2014-09-18

申请号：US13827253

申请日：2013-03-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Christian Hecht ,  Tobias Hoechbauer ,  Roland Rupp ,  Hans-Joachim Schulze

IPC: H01L21/02 ,  H01L29/16

CPC classification number: H01L21/02529 ,  H01L21/76254 ,  H01L29/1608

Abstract: A method for manufacturing a silicon carbide substrate for an electrical silicon carbide device includes providing a silicon carbide dispenser wafer including a silicon face and a carbon face and depositing a silicon carbide epitaxial layer on the silicon face. Further, the method includes implanting ions with a predefined energy characteristic forming an implant zone within the epitaxial layer, so that the ions are implanted with an average depth within the epitaxial layer corresponding to a designated thickness of an epitaxial layer of the silicon carbide substrate to be manufactured. Furthermore, the method comprises bonding an acceptor wafer onto the epitaxial layer so that the epitaxial layer is arranged between the dispenser wafer and the acceptor wafer. Further, the epitaxial layer is split along the implant zone so that a silicon carbide substrate represented by the acceptor wafer with an epitaxial layer with the designated thickness is obtained.

Abstract translation: 一种用于制造用于电碳化硅器件的碳化硅衬底的方法包括提供包括硅面和碳面的碳化硅分配器晶片，并在硅表面上沉积碳化硅外延层。 此外，该方法包括以预定的能量特性注入离子，在外延层内形成注入区，使得离子注入到外延层内的对应于碳化硅衬底外延层的指定厚度的平均深度， 制造。 此外，该方法包括将受体晶片结合到外延层上，使得外延层布置在分配器晶片和受主晶片之间。 此外，外延层沿着注入区域分裂，从而获得由具有指定厚度的外延层的受主晶片表示的碳化硅衬底。

公开(公告)号：US20220005742A1

公开(公告)日：2022-01-06

申请号：US17481459

申请日：2021-09-22

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Christian Hecht ,  Roland Rupp ,  Andre Kabakow

IPC: H01L23/31 ,  H01L29/739 ,  H01L29/78 ,  H01L29/808 ,  H01L29/861 ,  H01L29/06 ,  H01L29/10 ,  H01L21/02 ,  H01L21/28 ,  H01L21/283 ,  H01L21/308 ,  H01L21/56 ,  H01L23/29 ,  H01L27/06 ,  H01L29/47 ,  H01L29/66 ,  H01L29/70 ,  H01L29/872

Abstract: A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers include outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer.

公开(公告)号：US11158557B2

公开(公告)日：2021-10-26

申请号：US16394803

申请日：2019-04-25

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Christian Hecht ,  Roland Rupp ,  Andre Kabakow

IPC: H01L23/31 ,  H01L29/739 ,  H01L29/78 ,  H01L29/808 ,  H01L29/861 ,  H01L29/06 ,  H01L29/10 ,  H01L21/02 ,  H01L21/28 ,  H01L21/283 ,  H01L21/308 ,  H01L21/56 ,  H01L23/29 ,  H01L27/06 ,  H01L29/47 ,  H01L29/66 ,  H01L29/70 ,  H01L29/872 ,  H01L29/423

Abstract: A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers comprise outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer. The inner and outer edge sides of the third layer are closer to the outer edge side of the electrode than the respective inner and outer edge sides of the first and second layer.

公开(公告)号：US10411097B2

公开(公告)日：2019-09-10

申请号：US15868619

申请日：2018-01-11

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Jens Peter Konrath ,  Roland Rupp ,  Christian Hecht

IPC: H01L29/16 ,  H01L21/04 ,  H01L21/265 ,  H01L21/762 ,  H01L29/739 ,  H01L29/78

Abstract: Representative implementations of devices and techniques provide an optimized layer for a semiconductor component. In an example, a doped portion of a wafer, forming a substrate layer may be transferred from the wafer to an acceptor, or handle wafer. A component layer may be applied to the substrate layer. The acceptor wafer is detached from the substrate layer. In some examples, further processing may be executed with regard to the substrate and/or component layers.

公开(公告)号：US09035322B2

公开(公告)日：2015-05-19

申请号：US13850374

申请日：2013-03-26

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Christian Hecht ,  Roland Rupp ,  Rudolf Elpelt

IPC: H01L29/15 ,  H01L29/16 ,  H01L21/04 ,  H01L29/872 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/0623 ,  H01L21/046 ,  H01L21/2652 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

Abstract: A silicon carbide device includes an epitaxial silicon carbide layer including a first conductivity type and a buried lateral silicon carbide edge termination region located within the epitaxial silicon carbide layer including a second conductivity type. The buried lateral silicon carbide edge termination region is covered by a silicon carbide surface layer including the first conductivity type.

Abstract translation: 碳化硅器件包括包括第一导电类型的外延碳化硅层和位于包含第二导电类型的外延碳化硅层内的埋入横向碳化硅边缘终止区。 埋入的侧面碳化硅边缘终端区域由包括第一导电类型的碳化硅表面层覆盖。

公开(公告)号：US20140291697A1

公开(公告)日：2014-10-02

申请号：US14033631

申请日：2013-09-23

Applicant: Infineon Technologies AG

Inventor： Roland Rupp ,  Christian Hecht ,  Jens Konrath ,  Wolfgang Bergner ,  Hans-Joachim Schulze ,  Rudolf Elpelt

IPC: H01L29/16

CPC classification number: H01L29/1608 ,  H01L21/045 ,  H01L21/046 ,  H01L21/047 ,  H01L21/0495 ,  H01L21/565 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/3171 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7811 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A silicon carbide device includes a silicon carbide substrate, an inorganic passivation layer structure and a molding material layer. The inorganic passivation layer structure laterally covers at least partly a main surface of the silicon carbide substrate and the molding material layer is arranged adjacent to the inorganic passivation layer structure.

Abstract translation: 碳化硅器件包括碳化硅衬底，无机钝化层结构和成型材料层。 无机钝化层结构至少部分地覆盖碳化硅衬底的主表面，并且模制材料层被布置成与无机钝化层结构相邻。

公开(公告)号：US20140291695A1

公开(公告)日：2014-10-02

申请号：US13850374

申请日：2013-03-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Hans-Joachim Schulze ,  Christian Hecht ,  Roland Rupp ,  Rudolf Elpelt

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/265

CPC classification number: H01L29/0623 ,  H01L21/046 ,  H01L21/2652 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

Abstract: A silicon carbide device includes an epitaxial silicon carbide layer including a first conductivity type and a buried lateral silicon carbide edge termination region located within the epitaxial silicon carbide layer including a second conductivity type. The buried lateral silicon carbide edge termination region is covered by a silicon carbide surface layer including the first conductivity type.

Abstract translation: 碳化硅器件包括包括第一导电类型的外延碳化硅层和位于包含第二导电类型的外延碳化硅层内的埋入横向碳化硅边缘终止区。 埋入的侧面碳化硅边缘终端区域由包括第一导电类型的碳化硅表面层覆盖。