公开(公告)号：US11183445B2

公开(公告)日：2021-11-23

申请号：US16776026

申请日：2020-01-29

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Frank Daeche ,  Daniel Schleisser ,  Thomas Stoek

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/31 ,  H01L25/075 ,  H01L25/07 ,  H01L25/04 ,  H01L25/11 ,  H01L25/065

Abstract: A semiconductor arrangement comprises a leadframe comprising at least a first and a second carrier, the first and second carriers being arranged laterally besides each other, at least a first and a second semiconductor die, the first semiconductor die being arranged on and electrically coupled to the first carrier and the second semiconductor die being arranged on and electrically coupled to the second carrier, and an interconnection configured to mechanically fix the first carrier to the second carrier and to electrically insulate the first carrier from the second carrier, wherein the first and second semiconductor dies are at least partially exposed to the outside.

公开(公告)号：US20210127490A1

公开(公告)日：2021-04-29

申请号：US16663947

申请日：2019-10-25

Applicant: Infineon Technologies AG

Inventor： Petteri Palm ,  Martin Benisek ,  Liu Chen ,  Frank Daeche ,  Josef Maerz

IPC: H05K1/18 ,  H05K1/02 ,  H05K1/03

Abstract: A power electronic assembly includes a board having metal layers laminated onto or between electrically insulating layers, and a power device embedded in the board. A first metal layer provides electrical contacts at a first side of the board. A second metal layer provides a thermal contact at a second side of the board. A third metal layer is positioned between the first metal layer and the power device and configured to distribute a load current switched by the power device. A fourth metal layer is positioned between the second metal layer and the power device and configured as a primary thermal conduction path for heat generated by the power device during switching of the load current. A first electrically insulating layer separates the fourth metal layer from the second metal layer so that the fourth metal layer is electrically isolated from but thermally connected to the second metal layer.

公开(公告)号：US20210313273A1

公开(公告)日：2021-10-07

申请号：US17208363

申请日：2021-03-22

Applicant: Infineon Technologies AG

Inventor： Richard Knipper ,  Frank Daeche

IPC: H01L23/538 ,  H01L23/544 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78

Abstract: A method for fabricating a semiconductor package includes: providing a semiconductor wafer having opposing first and second sides, the semiconductor wafer being arranged on a first carrier such that the second side of the wafer faces the carrier; masking sawing lines on the first side of the semiconductor wafer with a mask; depositing a first metal layer on the masked first side of the semiconductor wafer by cold spraying or by high velocity oxygen fuel spraying or by cold plasma assisted deposition, such that the first metal layer does not cover the sawing lines, the deposited first metal layer having a thickness of 50 μm or more; singulating the semiconductor wafer into a plurality of semiconductor dies by sawing the semiconductor wafer along the sawing lines; and encapsulating the plurality of semiconductor dies with an encapsulant such that the first metal layer is exposed on a first side of the encapsulant.

公开(公告)号：US10186481B2

公开(公告)日：2019-01-22

申请号：US15459270

申请日：2017-03-15

Applicant: Infineon Technologies AG

Inventor： Maciej Wojnowski ,  Frank Daeche ,  Zeeshan Umar

IPC: H01L29/00 ,  H01L23/522 ,  H01L23/552 ,  H01F17/00 ,  H01L23/498 ,  H01L23/538 ,  H02M3/158

Abstract: A device includes a semiconductor chip, a plurality of planar metallization layers arranged over a main surface of the semiconductor chip, and a passive component including windings, wherein each of the windings is formed in one of the plurality of planar metallization layers.

公开(公告)号：US09425116B2

公开(公告)日：2016-08-23

申请号：US13656822

申请日：2012-10-22

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Frank Daeche

IPC: H01L23/12 ,  H01L21/52 ,  H01L23/50 ,  H01L23/13 ,  H05K1/18 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H05K3/46

CPC classification number: H01L23/12 ,  H01L21/52 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/16 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/24101 ,  H01L2224/24227 ,  H01L2224/73267 ,  H01L2224/82106 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/1431 ,  H01L2924/15153 ,  H01L2924/15311 ,  H05K1/186 ,  H05K3/4697 ,  H01L2924/00

Abstract: An integrated circuit package includes a package module including one or more circuit interconnections formed in a carrier, wherein at least one top-side package contact is formed over the top-side of the package module and electrically connected to at least one circuit interconnection of the one or more circuit interconnections and wherein a cavity is formed at the top-side of the package module; a chip disposed in the cavity, the chip including at least one chip front side contact and at least one chip back side contact, wherein the at least one chip front side contact is electrically connected to at least one further circuit interconnection of the one or more circuit interconnections; an electrically conductive structure connecting the at least one top-side package contact to the chip back side contact; and a metallic layer formed over the electrically conductive structure and on the chip back side contact.

Abstract translation: 集成电路封装包括封装模块，该封装模块包括形成在载体中的一个或多个电路互连，其中至少一个顶侧封装触点形成在封装模块的顶侧之上，并电连接到封装模块的至少一个电路互连 一个或多个电路互连，并且其中空腔形成在封装模块的顶侧; 设置在所述空腔中的芯片，所述芯片包括至少一个芯片前侧触点和至少一个芯片背面接触件，其中所述至少一个芯片前侧触点电连接到所述一个或多个芯片前侧触点的至少一个另外的电路互连 电路互连; 将所述至少一个顶侧封装触头连接到所述芯片背侧触点的导电结构; 以及形成在导电结构上和芯片背侧接触件上的金属层。

公开(公告)号：US20130082386A1

公开(公告)日：2013-04-04

申请号：US13656822

申请日：2012-10-22

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Frank Daeche

IPC: H01L23/12 ,  H01L23/50 ,  H01L21/52

CPC classification number: H01L23/12 ,  H01L21/52 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/16 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/24101 ,  H01L2224/24227 ,  H01L2224/73267 ,  H01L2224/82106 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/1431 ,  H01L2924/15153 ,  H01L2924/15311 ,  H05K1/186 ,  H05K3/4697 ,  H01L2924/00

Abstract: An integrated circuit package includes a package module including one or more circuit interconnections formed in a carrier, wherein at least one top-side package contact is formed over the top-side of the package module and electrically connected to at least one circuit interconnection of the one or more circuit interconnections and wherein a cavity is formed at the top-side of the package module; a chip disposed in the cavity, the chip including at least one chip front side contact and at least one chip back side contact, wherein the at least one chip front side contact is electrically connected to at least one further circuit interconnection of the one or more circuit interconnections; an electrically conductive structure connecting the at least one top-side package contact to the chip back side contact; and a metallic layer formed over the electrically conductive structure and on the chip back side contact.

Abstract translation: 集成电路封装包括封装模块，该封装模块包括形成在载体中的一个或多个电路互连，其中至少一个顶侧封装触点形成在封装模块的顶侧之上，并电连接到封装模块的至少一个电路互连 一个或多个电路互连，并且其中空腔形成在封装模块的顶侧; 设置在所述空腔中的芯片，所述芯片包括至少一个芯片前侧触点和至少一个芯片背面接触件，其中所述至少一个芯片前侧触点电连接到所述一个或多个芯片前侧触点的至少一个另外的电路互连 电路互连; 将所述至少一个顶侧封装触头连接到所述芯片背侧触点的导电结构; 以及形成在导电结构上和芯片背侧接触件上的金属层。