公开(公告)号：US09590091B2

公开(公告)日：2017-03-07

申请号：US14466198

申请日：2014-08-22

Applicant: Infineon Technologies AG

Inventor： Adrian Finney ,  Paolo Del Croce ,  Luca Petruzzi ,  Norbert Krischke

IPC: H01L27/108 ,  H01L29/78 ,  H01L27/06 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/7811 ,  H01L21/765 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0629 ,  H01L27/0922 ,  H01L29/0607 ,  H01L29/0688 ,  H01L29/7805

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a power device well in a semiconductor substrate, a logic device well in the substrate and spaced apart from the power device well by a separation region of the substrate, and a minority carrier conversion structure including a first doped region of a first conductivity type in the separation region, a second doped region of a second conductivity type in the separation region and a conducting layer connecting the first and second doped regions. The second doped region includes a first part interposed between the first doped region and the power device well and a second part interposed between the first doped region and the logic device well.

Abstract translation: 根据半导体器件的实施例，半导体器件在半导体衬底中包括良好的功率器件，在衬底中良好的逻辑器件，并且通过衬底的分离区与阱与阱的间隔开，并且少数载流子转换 在分离区域中包括第一导电类型的第一掺杂区域，在分离区域中具有第二导电类型的第二掺杂区域和连接第一和第二掺杂区域的导电层。 第二掺杂区域包括插入在第一掺杂区域和功率器件阱之间的第一部分和插入在第一掺杂区域和逻辑器件阱之间的第二部分。

公开(公告)号：US09245888B2

公开(公告)日：2016-01-26

申请号：US13631924

申请日：2012-09-29

Applicant: Infineon Technologies AG

Inventor： Luca Petruzzi ,  Bernhard Auer ,  Paolo Del Croce ,  Markus Ladurner

IPC: H01L29/78 ,  H01L27/092 ,  H01L27/02 ,  H03K17/0814 ,  H01L29/423

CPC classification number: H01L27/0922 ,  H01L27/0248 ,  H01L29/42368 ,  H01L29/7813 ,  H01L2924/0002 ,  H03K17/08142 ,  H01L2924/00

Abstract: A semiconductor device is disclosed. In accordance with a first aspect of the present invention the device includes a semiconductor chip having a substrate, a first supply terminal electrically coupled to the substrate to provide a first supply potential (VS) and a load current to the substrate, and a second supply terminal operably provided with a second supply potential. A first vertical transistor is integrated in the semiconductor chip and electrically coupled between the supply terminal and an output terminal. The first vertical transistor is configured to provide a current path for the load current to the output terminal in accordance with a control signal, which is provided to a gate electrode of the first vertical transistor.

Abstract translation: 公开了一种半导体器件。 根据本发明的第一方面，该器件包括具有衬底的半导体芯片，与衬底电耦合以提供第一电源电位（VS）和向衬底提供负载电流的第一电源端子，以及第二电源 端子可操作地设置有第二电源电位。 第一垂直晶体管集成在半导体芯片中并电耦合在电源端子和输出端子之间。 第一垂直晶体管被配置为根据提供给第一垂直晶体管的栅电极的控制信号为输出端提供负载电流的电流路径。

公开(公告)号：US20140292307A1

公开(公告)日：2014-10-02

申请号：US14305562

申请日：2014-06-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Peter Bogner ,  Luca Petruzzi

IPC: G01R19/00 ,  G01R1/20

CPC classification number: G01R19/0092 ,  G01R1/00 ,  G01R1/20 ,  H01L2221/00 ,  H02M1/00

Abstract: A circuit arrangement for measuring a load current provided to a load via a first load terminal of a load transistor is disclosed. In accordance with one example of the invention, the circuit arrangement includes a sense transistor coupled to the load transistor to provide a sense current representing the load current at a first load terminal of the sense transistor. The first load terminals of the load and the sense transistors are at respective floating electric potentials. A floating sense circuit coupled between the load terminals of sense transistor and load transistor, at least in one mode of operation the sense circuit receives the sense current and provides a floating signal representing the sense current. A non-floating measurement circuit is coupled to the sense circuit via a DC decoupling capacitor for transferring the floating signal representing the sense current to the non-floating measurement circuit. The measurement circuit is configured to provide an output signal representing the floating signal and thus the sense current.

Abstract translation: 公开了一种用于测量通过负载晶体管的第一负载端子提供给负载的负载电流的电路装置。 根据本发明的一个示例，电路装置包括耦合到负载晶体管的检测晶体管，以提供表示感测晶体管的第一负载端子处的负载电流的感测电流。 负载和感测晶体管的第一负载端子处于相应的浮置电位。 耦合在感测晶体管和负载晶体管的负载端子之间的浮动感测电路，至少在一种工作模式中，感测电路接收检测电流并提供表示感测电流的浮置信号。 非浮动测量电路经由用于将表示感测电流的浮动信号传送到非浮动测量电路的DC去耦电容耦合到感测电路。 测量电路被配置为提供表示浮置信号和因此感测电流的输出信号。

公开(公告)号：US09594097B2

公开(公告)日：2017-03-14

申请号：US14305562

申请日：2014-06-16

Applicant: Infineon Technologies AG

Inventor： Peter Bogner ,  Luca Petruzzi

IPC: G01R1/20 ,  G01R19/00 ,  H02M1/00 ,  G01R1/00

CPC classification number: G01R19/0092 ,  G01R1/00 ,  G01R1/20 ,  H01L2221/00 ,  H02M1/00

Abstract: A circuit arrangement for measuring a load current provided to a load via a first load terminal of a load transistor is disclosed. In accordance with one example of the invention, the circuit arrangement includes a sense transistor coupled to the load transistor to provide a sense current representing the load current at a first load terminal of the sense transistor. The first load terminals of the load and the sense transistors are at respective floating electric potentials. A floating sense circuit coupled between the load terminals of sense transistor and load transistor, at least in one mode of operation the sense circuit receives the sense current and provides a floating signal representing the sense current. A non-floating measurement circuit is coupled to the sense circuit via a DC decoupling capacitor for transferring the floating signal representing the sense current to the non-floating measurement circuit. The measurement circuit is configured to provide an output signal representing the floating signal and thus the sense current.

Abstract translation: 公开了一种用于测量通过负载晶体管的第一负载端子提供给负载的负载电流的电路装置。 根据本发明的一个示例，电路装置包括耦合到负载晶体管的检测晶体管，以提供表示感测晶体管的第一负载端子处的负载电流的感测电流。 负载和感测晶体管的第一负载端子处于相应的浮置电位。 耦合在感测晶体管的负载端子和负载晶体管之间的浮动感测电路，至少在一种工作模式中，感测电路接收感测电流并提供表示感测电流的浮置信号。 非浮动测量电路经由用于将表示感测电流的浮动信号传送到非浮动测量电路的DC去耦电容耦合到感测电路。 测量电路被配置为提供表示浮置信号和因此感测电流的输出信号。

公开(公告)号：US20160248242A1

公开(公告)日：2016-08-25

申请号：US14629907

申请日：2015-02-24

Applicant: Infineon Technologies AG

Inventor： Luca Petruzzi ,  Bernhard Schaffer ,  Florian Brugger ,  Mario Tripolt

IPC: H02H3/08 ,  H02H7/20 ,  H02H7/18 ,  H02H5/04

CPC classification number: H03K17/082

Abstract: According to an embodiment, a fault protection system includes a first power supply terminal, a second power supply terminal, an error circuit configured to receive a power supply signal, and a power supply circuit coupled to the error circuit, the first power supply terminal, and the second power supply terminal. The power supply circuit is configured to provide the power supply signal from the first power supply terminal during a first operation mode and provide the power supply signal from the second power supply terminal during a second operation mode.

Abstract translation: 根据实施例，故障保护系统包括第一电源端子，第二电源端子，被配置为接收电源信号的误差电路，以及耦合到误差电路的电源电路，第一电源端子， 和第二电源端子。 电源电路被配置为在第一操作模式期间提供来自第一电源端子的电源信号，并且在第二操作模式期间提供来自第二电源端子的电源信号。

公开(公告)号：US20150092307A1

公开(公告)日：2015-04-02

申请号：US14042155

申请日：2013-09-30

Applicant: Infineon Technologies AG

Inventor： Luca Petruzzi

IPC: H02H9/04

CPC classification number: H02H9/041 ,  H01L21/761 ,  H01L27/0248 ,  H01L27/0921 ,  H01L27/0922 ,  H01L29/7835 ,  H01L29/866 ,  H02H9/043

Abstract: A semiconductor device is disclosed. In one embodiment a semiconductor device includes a semiconductor chip including a substrate, a ground terminal configured to be provided with a reference potential and a supply terminal electrically coupled to the substrate, the supply terminal configured to be provided with a load current and configured to be provided with a supply voltage between the substrate and the ground terminal. The semiconductor device further comprises an overvoltage protection circuit disposed in the semiconductor chip and coupled between the supply terminal and the ground terminal, the overvoltage protection circuit including a first transistor having a load current path coupled between the supply terminal and an internal ground node and a second transistor having a load current path coupled between the internal ground node and the ground terminal.

Abstract translation: 公开了一种半导体器件。 在一个实施例中，半导体器件包括：半导体芯片，其包括衬底，配置成具有参考电位的接地端子和电耦合到衬底的供电端子，所述供电端子被配置为具有负载电流并且被配置为 在基板和接地端子之间提供电源电压。 所述半导体器件还包括设置在所述半导体芯片中并耦合在所述电源端子和所述接地端子之间的过电压保护电路，所述过电压保护电路包括第一晶体管，所述第一晶体管具有耦合在所述电源端子和内部接地节点之间的负载电流路径， 第二晶体管具有耦合在内部接地节点和接地端子之间的负载电流路径。

公开(公告)号：US20140091384A1

公开(公告)日：2014-04-03

申请号：US13631924

申请日：2012-09-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Luca Petruzzi ,  Bernhard Auer ,  Paolo Del Croce ,  Markus Ladurner

IPC: H01L29/78

CPC classification number: H01L27/0922 ,  H01L27/0248 ,  H01L29/42368 ,  H01L29/7813 ,  H01L2924/0002 ,  H03K17/08142 ,  H01L2924/00

Abstract: A semiconductor device is disclosed. In accordance with a first aspect of the present invention the device includes a semiconductor chip having a substrate, a first supply terminal electrically coupled to the substrate to provide a first supply potential (VS) and a load current to the substrate, and a second supply terminal operably provided with a second supply potential. A first vertical transistor is integrated in the semiconductor chip and electrically coupled between the supply terminal and an output terminal. The first vertical transistor is configured to provide a current path for the load current to the output terminal in accordance with a control signal, which is provided to a gate electrode of the first vertical transistor.

Abstract translation: 公开了一种半导体器件。 根据本发明的第一方面，该器件包括具有衬底的半导体芯片，与衬底电耦合以提供第一电源电位（VS）和向衬底提供负载电流的第一电源端子，以及第二电源 端子可操作地设置有第二电源电位。 第一垂直晶体管集成在半导体芯片中并电耦合在电源端子和输出端子之间。 第一垂直晶体管被配置为根据提供给第一垂直晶体管的栅电极的控制信号为输出端提供负载电流的电流路径。