公开(公告)号：US09673320B2

公开(公告)日：2017-06-06

申请号：US15182120

申请日：2016-06-14

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7819 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825

Abstract: A transistor cell includes a drift region, a source region, a body region, and a drain region that is laterally spaced apart from the source region. A gate electrode is adjacent the body region. A field electrode is arranged in the drift region. A source electrode is connected to the source region and the body region, and a drain electrode is connected to the drain region. An avalanche bypass structure is coupled between the source electrode and the drain electrode and includes a first semiconductor layer of the first doping type, a second semiconductor layer of the first doping type, and a pn-junction arranged between the first semiconductor layer and the source electrode. The second semiconductor layer has a higher doping concentration than the first semiconductor layer and is arranged between the second semiconductor layer and the drift region. The drain electrode is electrically connected to the second semiconductor layer.

公开(公告)号：US09530884B2

公开(公告)日：2016-12-27

申请号：US14868909

申请日：2015-09-29

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L29/417 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L29/7825 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7835

Abstract: A method of manufacturing a semiconductor device including a transistor comprises forming field plate trenches in a main surface of a semiconductor substrate, a drift zone being defined between adjacent field plate trenches, forming a field dielectric layer in the field plate trenches, thereafter, forming gate trenches in the main surface of the semiconductor substrate, a channel region being defined between adjacent gate trenches, and forming a conductive material in at least some of the field plate trenches and in at least some of the gate trenches. The method further comprising forming a source region and forming a drain region in the main surface of the semiconductor substrate.

Abstract translation: 制造包括晶体管的半导体器件的方法包括在半导体衬底的主表面中形成场板沟槽，在相邻的场板沟槽之间限定漂移区，在场板栅沟中形成场介电层，之后形成栅极 在半导体衬底的主表面中的沟槽，沟道区域被限定在相邻栅极沟槽之间，并且在至少一些场板沟槽和至少一些栅极沟槽中形成导电材料。 该方法还包括形成源极区域并在半导体衬底的主表面中形成漏极区域。

公开(公告)号：US20160322357A1

公开(公告)日：2016-11-03

申请号：US15138739

申请日：2016-04-26

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H05B33/08 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/266 ,  H01L29/417 ,  H01L29/423

CPC classification number: H05B33/083 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66659 ,  H01L29/78

Abstract: A semiconductor device includes first and second field effect transistors (FETs) formed in a semiconductor substrate having a first main surface. The first FET includes first source and drain contact grooves, each running in a first direction parallel to the first main surface, each formed in the first main surface. First source regions are electrically connected to a conductive material in the first source contact groove. First drain regions are electrically connected to a conductive material in the first drain contact groove. The second FET includes second source and drain contact grooves, each running in a second direction parallel to the first main surface, each formed in the first main surface. Second source regions are electrically connected to a conductive material in the second source contact groove, and second drain regions are electrically connected to a conductive material in the second drain contact groove.

Abstract translation: 半导体器件包括形成在具有第一主表面的半导体衬底中的第一和第二场效应晶体管（FET）。 第一FET包括第一源极和漏极接触槽，每个沿着平行于第一主表面的第一方向延伸，每个形成在第一主表面中。 第一源极区域与第一源极接触槽中的导电材料电连接。 第一漏极区电连接到第一漏极接触槽中的导电材料。 第二FET包括第二源极和漏极接触槽，每个在与第一主表面平行的第二方向上延伸，每个形成在第一主表面中。 第二源极区域与第二源极接触槽中的导电材料电连接，并且第二漏极区域电连接到第二漏极接触槽中的导电材料。

公开(公告)号：US20160268397A1

公开(公告)日：2016-09-15

申请号：US15160525

申请日：2016-05-20

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Thorsten Meyer

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L21/28 ,  H01L21/76

CPC classification number: H01L29/66704 ,  H01L21/28008 ,  H01L21/76 ,  H01L21/761 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66659 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7835

Abstract: A method of manufacturing a semiconductor device includes forming a transistor in a semiconductor substrate having a first main surface. The transistor is formed by forming a source region, forming a drain region, forming a channel region, forming a drift zone, and forming a gate electrode adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface, between the source region and the drain region. Forming the semiconductor device further includes forming a conductive layer, a portion of the conductive layer being disposed beneath the gate electrode and insulated from the gate electrode.

公开(公告)号：US09349834B2

公开(公告)日：2016-05-24

申请号：US14794898

申请日：2015-07-09

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Thorsten Meyer

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/66704 ,  H01L21/28008 ,  H01L21/76 ,  H01L21/761 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66659 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7835

Abstract: A method of manufacturing a semiconductor device includes forming a transistor in a semiconductor substrate having a first main surface. The transistor is formed by forming a source region, forming a drain region, forming a channel region, forming a drift zone, and forming a gate electrode adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface, between the source region and the drain region. Forming the semiconductor device further includes forming a conductive layer, a portion of the conductive layer being disposed beneath the gate electrode and insulated from the gate electrode.

Abstract translation: 制造半导体器件的方法包括在具有第一主表面的半导体衬底中形成晶体管。 晶体管通过形成源极区域，形成漏极区域，形成沟道区域，形成漂移区域以及形成与沟道区域的至少两侧相邻的栅电极而形成。 沟道区域和漂移区沿着平行于第一主表面的第一方向，在源极区域和漏极区域之间设置。 形成半导体器件还包括形成导电层，导电层的一部分设置在栅电极下方并与栅电极绝缘。

公开(公告)号：US20150311317A1

公开(公告)日：2015-10-29

申请号：US14794898

申请日：2015-07-09

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Thorsten Meyer

IPC: H01L29/66 ,  H01L21/28

CPC classification number: H01L29/66704 ,  H01L21/28008 ,  H01L21/76 ,  H01L21/761 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66659 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7835

Abstract: A method of manufacturing a semiconductor device includes forming a transistor in a semiconductor substrate having a first main surface. The transistor is formed by forming a source region, forming a drain region, forming a channel region, forming a drift zone, and forming a gate electrode adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface, between the source region and the drain region. Forming the semiconductor device further includes forming a conductive layer, a portion of the conductive layer being disposed beneath the gate electrode and insulated from the gate electrode.

Abstract translation: 制造半导体器件的方法包括在具有第一主表面的半导体衬底中形成晶体管。 晶体管通过形成源极区域，形成漏极区域，形成沟道区域，形成漂移区域以及形成与沟道区域的至少两侧相邻的栅电极而形成。 沟道区域和漂移区沿着平行于第一主表面的第一方向，在源极区域和漏极区域之间设置。 形成半导体器件还包括形成导电层，导电层的一部分设置在栅电极下方并与栅电极绝缘。

公开(公告)号：US20150102404A1

公开(公告)日：2015-04-16

申请号：US14053633

申请日：2013-10-15

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Franz Hirler

IPC: H01L29/78 ,  H01L29/40

CPC classification number: H01L29/7813 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7838 ,  H01L29/8083

Abstract: A semiconductor device includes a transistor formed in a semiconductor substrate including a main surface. The transistor includes a source region, a drain region, a channel region, and a gate electrode. The source region and the drain region are disposed along a first direction, the first direction being parallel to the main surface. The channel region has a shape of a ridge extending along the first direction, the ridge including a top side and a first and a second sidewalls. The gate electrode is disposed at the first sidewall of the channel region, and the gate electrode is absent from the second sidewall of the channel region.

Abstract translation: 半导体器件包括形成在包括主表面的半导体衬底中的晶体管。 晶体管包括源极区，漏极区，沟道区和栅电极。 源极区域和漏极区域沿着第一方向设置，第一方向平行于主表面。 沟道区具有沿着第一方向延伸的脊的形状，脊包括顶侧和第一和第二侧壁。 栅电极设置在沟道区的第一侧壁处，栅电极不存在于沟道区的第二侧壁。

公开(公告)号：US20140346590A1

公开(公告)日：2014-11-27

申请号：US13902151

申请日：2013-05-24

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Franz Hirler

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/66204 ,  H01L29/66734 ,  H01L29/7391

Abstract: A semiconductor device formed in a semiconductor substrate includes a source region, a drain region, a gate electrode, and a body region disposed between the source region and the drain region. The gate electrode is disposed adjacent at least two sides of the body region, and the source region and the gate electrode are coupled to a source terminal. A width of the body region between the two sides of the body region is selected so that the body region is configured to be fully depleted.

Abstract translation: 形成在半导体衬底中的半导体器件包括源极区，漏极区，栅电极和设置在源极区和漏极区之间的体区。 栅电极被设置在身体区域的至少两侧附近，并且源极区域和栅极电极耦合到源极端子。 选择身体区域的两侧之间的身体区域的宽度，使得身体区域被配置为完全耗尽。

公开(公告)号：US08860136B2

公开(公告)日：2014-10-14

申请号：US13692397

申请日：2012-12-03

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L27/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/66666 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825 ,  H01L29/785

Abstract: A semiconductor device includes a transistor, formed in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode being adjacent to the channel region, the gate electrode configured to control a conductivity of a channel formed in the channel region. The channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a ridge extending along the first direction and the drift zone including a superjunction layer stack.

Abstract translation: 半导体器件包括形成在具有第一主表面的半导体衬底中的晶体管。 所述晶体管包括源极区，漏极区，沟道区，漂移区以及与所述沟道区相邻的栅极，所述栅电极被配置为控制在所述沟道区中形成的沟道的导电性。 沟道区域和漂移区域沿着源极区域和漏极区域之间的第一方向设置，第一方向平行于第一主表面。 沟道区具有沿着第一方向延伸的脊的形状，并且漂移区包括超结层层叠。

公开(公告)号：US10381477B2

公开(公告)日：2019-08-13

申请号：US15653639

申请日：2017-07-19

Applicant: Infineon Technologies AG

Inventor： Andreas Peter Meiser ,  Till Schloesser

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417

Abstract: A semiconductor device in a semiconductor substrate having a first main surface includes a transistor array and a termination region. The transistor array includes a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel in the body region. The body region and the drift zone are disposed along a first horizontal direction between the source region and the drain region. The transistor array further includes first field plate trenches in the drift zone. A longitudinal axis of the first field plate trenches extends in the first horizontal direction. The semiconductor device further includes a second field plate trench, a longitudinal axis of the second field plate trench extending in a second horizontal direction perpendicular to the first direction.