公开(公告)号：US20160380063A1

公开(公告)日：2016-12-29

申请号：US15189147

申请日：2016-06-22

Applicant: Infineon Technologies AG

Inventor： Franz Hirler ,  Anton Mauder ,  Hermann Gruber ,  Hubert Rothleitner ,  Andreas Peter Meiser

IPC: H01L29/40

CPC classification number: H01L29/407 ,  H01L21/76224 ,  H01L21/76898 ,  H01L21/823481 ,  H01L23/481 ,  H01L24/16 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/402 ,  H01L29/408 ,  H01L29/41741 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2224/16245 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method for producing a semiconductor component is provided. The method includes providing a semiconductor body with a first surface and a second surface opposite to the first surface, etching an insulation trench from the first surface partially into the semiconductor body, forming a first insulation layer on one or more sidewalls of the insulation trench, processing the second surface by at least one of grinding, polishing and a CMP-process to expose the first insulation layer, and depositing on the processed second surface a second insulation layer which extends to the first insulation layer.

Abstract translation: 提供一种半导体元件的制造方法。 该方法包括：提供具有与第一表面相对的第一表面和第二表面的半导体本体，将绝缘沟槽从第一表面部分地蚀刻到半导体本体中，在绝缘沟槽的一个或多个侧壁上形成第一绝缘层， 通过研磨，抛光和CMP工艺中的至少一个来处理第二表面以暴露第一绝缘层，以及在经处理的第二表面上沉积延伸到第一绝缘层的第二绝缘层。

公开(公告)号：US20140299972A1

公开(公告)日：2014-10-09

申请号：US14249642

申请日：2014-04-10

Applicant: Infineon Technologies AG

Inventor： Hermann Gruber ,  Thomas Gross ,  Andreas Peter Meiser ,  Markus Zundel

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/6835 ,  H01L21/76224 ,  H01L21/76898 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate having a first side and a second side opposite the first side, an active area and a through contact area, the active area including a transistor structure having a control electrode, the through contact area including a semiconductor mesa having insulated sidewalls. The semiconductor device further includes a first metallization on the first side in the active area and a recess extending from the first side into the semiconductor substrate and between the active area and the through contact area and including in the through contact area a horizontally widening portion, the recess being at least partly filled with a conductive material forming a first conductive region in ohmic contact with the semiconductor mesa and the transistor structure. The semiconductor device also includes a control metallization on the second side and in ohmic contact with the semiconductor mesa.

Abstract translation: 半导体器件包括具有第一侧和与第一侧相对的第二侧的半导体衬底，有源区和贯通接触区，所述有源区包括具有控制电极的晶体管结构，所述贯通接触区包括半导体台面，所述半导体衬底具有 绝缘侧壁。 所述半导体器件还包括在所述有源区域中的第一侧上的第一金属化和从所述第一侧延伸到所述半导体衬底中以及在所述有源区域和所述贯穿接触区域之间并且在所述贯穿接触区域中包括水平扩大部分的凹部， 所述凹部至少部分地填充有形成与所述半导体台面和所述晶体管结构欧姆接触的第一导电区域的导电材料。 半导体器件还包括在第二侧上的控制金属化并与半导体台面欧姆接触。

公开(公告)号：US11195946B2

公开(公告)日：2021-12-07

申请号：US17172680

申请日：2021-02-10

Applicant: Infineon Technologies AG

Inventor： Andreas Peter Meiser ,  Romain Esteve ,  Roland Rupp

IPC: H01L21/04 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/739 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L29/417 ,  H01L29/04 ,  H01L29/872

Abstract: A method of manufacturing semiconductor devices includes: forming source regions of a first conductivity type in a SiC-based semiconductor substrate, wherein dopants are introduced selectively through first segments of first mask openings in a first dopant mask and wherein a longitudinal axis of the first mask opening extends into a first horizontal direction; forming pinning regions of a complementary second conductivity type, wherein dopants are selectively introduced through second segments of the first mask openings and wherein the first and second segments alternate along the first horizontal direction; and forming body regions of the second conductivity type, wherein dopants are selectively introduced through second mask openings in a second dopant mask, wherein a width of the second mask openings along a second horizontal direction orthogonal to the first horizontal direction is greater than a width of the first mask openings.

公开(公告)号：US20180026133A1

公开(公告)日：2018-01-25

申请号：US15653639

申请日：2017-07-19

Applicant: Infineon Technologies AG

Inventor： Andreas Peter Meiser ,  Till Schloesser

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7833 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/66575 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7823 ,  H01L29/7825 ,  H01L29/7851

Abstract: A semiconductor device in a semiconductor substrate having a first main surface includes a transistor array and a termination region. The transistor array includes a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel in the body region. The body region and the drift zone are disposed along a first horizontal direction between the source region and the drain region. The transistor array further includes first field plate trenches in the drift zone. A longitudinal axis of the first field plate trenches extends in the first horizontal direction. The semiconductor device further includes a second field plate trench, a longitudinal axis of the second field plate trench extending in a second horizontal direction perpendicular to the first direction.

公开(公告)号：US09299829B2

公开(公告)日：2016-03-29

申请号：US14682755

申请日：2015-04-09

Applicant: Infineon Technologies AG

Inventor： Andreas Peter Meiser ,  Markus Zundel ,  Christoph Kadow

IPC: H01L29/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L29/7813 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7827

Abstract: A vertical transistor component includes a semiconductor body with first and second surfaces, a drift region, and a source region and body region arranged between the drift region and the first surface. The body region is also arranged between the source region and the drift region. The vertical transistor component further includes a gate electrode arranged adjacent to the body zone, a gate dielectric arranged between the gate electrode and the body region, and a drain region arranged between the drift region and the second surface. A source electrode electrically contacts the source region, is electrically insulated from the gate electrode and arranged on the first surface. A drain electrode electrically contacts the drain region and is arranged on the second surface. A gate contact electrode is electrically insulated from the semiconductor body, extends in the semiconductor body to the second surface, and is electrically connected with the gate electrode.

公开(公告)号：US08941217B2

公开(公告)日：2015-01-27

申请号：US14249642

申请日：2014-04-10

Applicant: Infineon Technologies AG

Inventor： Hermann Gruber ,  Thomas Gross ,  Andreas Peter Meiser ,  Markus Zundel

IPC: H01L29/40 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L21/6835 ,  H01L21/76224 ,  H01L21/76898 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate having a first side and a second side opposite the first side, an active area and a through contact area, the active area including a transistor structure having a control electrode, the through contact area including a semiconductor mesa having insulated sidewalls. The semiconductor device further includes a first metallization on the first side in the active area and a recess extending from the first side into the semiconductor substrate and between the active area and the through contact area and including in the through contact area a horizontally widening portion, the recess being at least partly filled with a conductive material forming a first conductive region in ohmic contact with the semiconductor mesa and the transistor structure. The semiconductor device also includes a control metallization on the second side and in ohmic contact with the semiconductor mesa.

Abstract translation: 半导体器件包括具有第一侧和与第一侧相对的第二侧的半导体衬底，有源区和贯通接触区，所述有源区包括具有控制电极的晶体管结构，所述贯通接触区包括半导体台面，所述半导体衬底具有 绝缘侧壁。 所述半导体器件还包括在所述有源区域中的第一侧上的第一金属化和从所述第一侧延伸到所述半导体衬底中以及在所述有源区域和所述贯穿接触区域之间并且在所述贯穿接触区域中包括水平扩大部分的凹部， 所述凹部至少部分地填充有形成与所述半导体台面和所述晶体管结构欧姆接触的第一导电区域的导电材料。 半导体器件还包括在第二侧上的控制金属化并与半导体台面欧姆接触。

公开(公告)号：US20210226015A1

公开(公告)日：2021-07-22

申请号：US17223645

申请日：2021-04-06

Applicant: Infineon Technologies AG

Inventor： Andreas Peter Meiser ,  Caspar Leendertz ,  Anton Mauder

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/808 ,  H01L29/739 ,  H01L29/40 ,  H01L29/423 ,  H01L21/308 ,  H01L21/31 ,  H01L21/04 ,  H01L21/311 ,  H01L21/426 ,  H01L21/02 ,  H01L21/033

Abstract: A silicon carbide substrate has a trench extending from a main surface of the silicon carbide substrate into the silicon carbide substrate. The trench has a trench width at a trench bottom. A shielding region is formed in the silicon carbide substrate. The shielding region extends along the trench bottom. In at least one doping plane extending approximately parallel to the trench bottom, a dopant concentration in the shielding region over a lateral first width deviates by not more than 10% from a maximum value of the dopant concentration. The first width is less than the trench width and is at least 30% of the trench width.

公开(公告)号：US20210050434A1

公开(公告)日：2021-02-18

申请号：US17085426

申请日：2020-10-30

Applicant: Infineon Technologies AG

Inventor： Gerhard Prechtl ,  Andreas Peter Meiser ,  Thomas Ostermann

IPC: H01L29/735 ,  H01L29/66 ,  H01L29/10 ,  H01L27/082

Abstract: An integrated circuit includes a semiconductor substrate, first and second doping regions in the substrate, a first insulating layer on a first surface of the semiconductor substrate, the first insulating layer having first and second openings above the first and second doping regions, a polysilicon layer on the first insulating layer, the polysilicon layer having first and second openings above the first and second openings of the first insulating layer, a second insulating layer on the polysilicon layer and having first and second openings above the first and second openings of the polysilicon layer, a first contact element disposed in the first openings, a second contact element disposed in the second openings, the first and second contact elements being in contact with the first and second doping regions.

公开(公告)号：US10381477B2

公开(公告)日：2019-08-13

申请号：US15653639

申请日：2017-07-19

Applicant: Infineon Technologies AG

Inventor： Andreas Peter Meiser ,  Till Schloesser

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417

Abstract: A semiconductor device in a semiconductor substrate having a first main surface includes a transistor array and a termination region. The transistor array includes a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel in the body region. The body region and the drift zone are disposed along a first horizontal direction between the source region and the drain region. The transistor array further includes first field plate trenches in the drift zone. A longitudinal axis of the first field plate trenches extends in the first horizontal direction. The semiconductor device further includes a second field plate trench, a longitudinal axis of the second field plate trench extending in a second horizontal direction perpendicular to the first direction.

公开(公告)号：US20230148156A1

公开(公告)日：2023-05-11

申请号：US18095260

申请日：2023-01-10

Applicant: Infineon Technologies AG

Inventor： Andreas Peter Meiser ,  Caspar Leendertz ,  Anton Mauder

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/808 ,  H01L29/739 ,  H01L29/40 ,  H01L29/423 ,  H01L21/308 ,  H01L21/31 ,  H01L21/04 ,  H01L21/311 ,  H01L21/426 ,  H01L21/02 ,  H01L21/033

CPC classification number: H01L29/1608 ,  H01L29/66924 ,  H01L29/0615 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/7397 ,  H01L29/0623 ,  H01L29/407 ,  H01L29/66348 ,  H01L29/4236 ,  H01L21/3083 ,  H01L21/31 ,  H01L21/0415 ,  H01L21/311 ,  H01L21/426 ,  H01L21/046 ,  H01L21/02019 ,  H01L21/0334

Abstract: A semiconductor component includes: a SiC semiconductor body; a trench extending from a first surface of the SiC semiconductor body into the SiC semiconductor body, the trench having a conductive connection structure, a structure width at a bottom of the trench, and a dielectric layer covering sidewalls of the trench; a shielding region along the bottom and having a central section which has a lateral first width; and a contact formed between the conductive connection structure and the shielding region. The conductive connection structure is electrically connected to a source electrode. In at least one doping plane extending approximately parallel to the bottom, a dopant concentration in the central section deviates by not more than 10% from a maximum value of the dopant concentration in the shielding region in the doping plane. The first width is less than the structure width and is at least 30% of the structure width.