公开(公告)号：US11722128B2

公开(公告)日：2023-08-08

申请号：US17357456

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Aaron Martin ,  Roger Cheng ,  Hari Venkatramani ,  Navneet Dour ,  Mozhgan Mansuri ,  Bryan Casper ,  Frank O'Mahony ,  Ganesh Balamurugan ,  Ajay Balankutty ,  Kuan Zhou ,  Sridhar Tirumalai ,  Krishnamurthy Venkataramana ,  Alex Thomas ,  Quoc Nguyen

IPC: H03K5/156 ,  H03L7/081 ,  G11C7/22 ,  G06F1/08 ,  G11C7/10

CPC classification number: H03K5/1565 ,  G06F1/08 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222 ,  H03L7/0812

Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

公开(公告)号：US20220147482A1

公开(公告)日：2022-05-12

申请号：US17338512

申请日：2021-06-03

Applicant: Intel Corporation

Inventor： Jihwan Kim ,  Ajay Balankutty ,  Sandipan Kundu ,  Stephen Kim ,  Frank O'Mahony ,  Kai Yu ,  Bong Chan Kim

IPC: G06F13/42 ,  H03K17/687 ,  G06F1/10 ,  G06F1/06

Abstract: An apparatus enables a high-bandwidth 4-way data serializing (4:1 serializer) digital-to-analog converter. The apparatus uses active inductor-based bandwidth extension technique for two-stage driver enabling design of quarter-rate 4-way data serializing transmitter. The 4:1 serializer output bandwidth is extended by gate-resistor-peaked n-type transistor load working as an active inductor. A current steering switch with current source is used as the final driver. The 4:1 serializer includes a pulse width tuning technique with tunable ground voltage on the ground terminal of a pulse generator to tune an effective threshold voltage of the pulse generator. A Bessel-like LC filter is coupled to an output of the 4:1 serializer. The filter includes shunt peaking paths that provide zeros, which natively cancel large parasitic capacitance at a shunt peaking node. As such, active and passive devices including driver circuitry, ESD diodes, and any other sensing circuitry are flexibly added on any LC filter nodes.

公开(公告)号：US11108433B2

公开(公告)日：2021-08-31

申请号：US16206919

申请日：2018-11-30

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Georgios Dogiamis ,  Jeff C. Morriss ,  Hyung-Jin Lee ,  Richard Dischler ,  Ajay Balankutty ,  Telesphor Kamgaing ,  Said Rami

IPC: H04B3/52 ,  H04L27/36

Abstract: Embodiments herein may relate to an interconnect that includes a transceiver, wherein the transceiver is configured to generate a single side band (SSB) signal for communication over a waveguide and a waveguide interconnect to communicate the SSB signal over the waveguide. In an example, an SSB operator is configured to generate the SSB signal and the SSB signal can be generated by use of a finite-impulse response filter. Other embodiments may be described and/or claimed.