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11.发明授权公开(公告)号：US09971391B2
公开(公告)日：2018-05-15
申请号：US14757903
申请日：2015-12-23
Applicant: Intel Corporation
Inventor： Devadatta Bodas , Meenakshi Arunachalam , Ilya Sharapov , Charles R. Yount , Scott B. Huck , Ramakrishna Huggahalli , Justin J. Song , Brian J. Griffith , Muralidhar Rajappa , Lingdan (Linda) Zeng
CPC classification number: G06F1/3206 , G06F1/324 , G06F11/3428 , Y02D10/126
Abstract: A method of assessing energy efficiency of a High-performance computing (HPC) system, including: selecting a plurality of HPC workloads to run on a system under test (SUT) with one or more power constraints, wherein the SUT includes a plurality of HPC nodes in the HPC system, executing the plurality of HPC workloads on the SUT, and generating a benchmark metric for the SUT based on a baseline configuration for each selected HPC workload and a plurality of measured performance per power values for each executed workload at each selected power constraint is shown.
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公开(公告)号：US09933829B2
公开(公告)日：2018-04-03
申请号：US15258803
申请日：2016-09-07
Applicant: INTEL CORPORATION
Inventor： Brian J. Griffith , Viktor D. Vogman , Justin J. Song
CPC classification number: G06F1/3206 , G06F1/26 , G06F1/3209 , H04B3/546 , H04B3/548 , H04B3/56 , H04B2203/547 , H04B2203/5483 , H04B2203/5495 , H04H20/38 , H04L47/50 , Y04S40/146
Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.
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Patent Agency Ranking
公开(公告)号：US09268393B2
公开(公告)日：2016-02-23
申请号：US13997295
申请日：2012-11-30
Applicant: Intel Corporation
Inventor： Ankush Varma , Krishnakanth Sistla , Martin T. Rowland , Brian J. Griffith , Viktor D. Vogman , Joseph R. Doucette , Eric J. Dehaemer , Vivek Garg , Chris Poirier , Jeremy J. Shrall , Avinash N. Ananthakrishnan , Stephen H. Gunther
CPC classification number: G06F1/3234 , G06F1/06 , G06F1/324 , G06F8/4432 , Y02D10/126
Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括多个核心，每个核心各自独立地执行指令，多个图形引擎各自独立地执行图形操作; 以及功率控制单元，其耦合到所述多个核以控制所述处理器的功率消耗，其中所述功率控制单元包括功率偏移控制逻辑，以将所述处理器的功率消耗水平限制在高于限定功率极限以上 工作周期的占空比部分。 描述和要求保护其他实施例。
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公开(公告)号：US20190053397A1
公开(公告)日：2019-02-14
申请号：US15870721
申请日：2018-01-12
Applicant: Intel Corporation
Inventor： Thane M. Larson , Vasudevan Srinivasan , Murugasmy K. Nachimuthu , Brian J. Griffith
IPC: H05K7/14
Abstract: The present disclosure describes a number of embodiments related to devices, systems, and methods for identifying a location of a resource among a plurality of locations in a data center rack. A signal transmission medium may be disposed proximate to the plurality of locations to transmit a signal traversing the plurality of locations, with each resource in the rack having a sensor or transmitter portion that couples itself to the signal transmission medium at a point substantially at this resource location, or the location of the resource within the data center rack is identified based at least in part on the sensed signal.
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15.发明申请公开(公告)号：US20180232024A1
公开(公告)日：2018-08-16
申请号：US15846161
申请日：2017-12-18
Applicant: Intel Corporation
Inventor： Krishnakanth Sistla , Martin Rowland , Efraim Rotem , Brian J. Griffith , Ankush Varma , Anupama Suryanarayanan
CPC classification number: G06F1/26 , G06F1/3203 , G06F1/3243 , G06F1/329 , Y02D10/152 , Y02D10/24
Abstract: A processor is described that includes a quick signal path from an input of the processor to logic circuitry within the processor. The input is to receive a fast throttle down signal. The logic circuitry is to throttle down a rate at which the processor issues instructions for execution in response to the fast throttle down signal. The quick signal path is to impose practicably minimal propagation delay of the fast throttle down signal within the processor.
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公开(公告)号：US20180188790A1
公开(公告)日：2018-07-05
申请号：US15906960
申请日：2018-02-27
Applicant: INTEL CORPORATION
Inventor： Brian J. Griffith , Viktor D. Vogman , Justin J. Song
CPC classification number: G06F1/3206 , G06F1/26 , G06F1/3209 , H04B3/546 , H04B3/548 , H04B3/56 , H04B2203/547 , H04B2203/5483 , H04B2203/5495 , H04H20/38 , H04L47/50 , Y04S40/146
Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.
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公开(公告)号：US20150381237A1
公开(公告)日：2015-12-31
申请号：US14319485
申请日：2014-06-30
Applicant: INTEL CORPORATION
Inventor： Brian J. Griffith , Viktor D. Vogman , Justin J. Song
CPC classification number: G06F1/3206 , G06F1/26 , G06F1/3209 , H04B3/546 , H04B3/548 , H04B3/56 , H04B2203/547 , H04B2203/5483 , H04B2203/5495 , H04H20/38 , H04L47/50 , Y04S40/146
Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.
Abstract translation: 服务器系统包括公用电源总线，用于通过公共电源总线提供直流（DC）电力的电源，至少一个节点，其包括处理器以通过公共电源总线接收DC电力;发射机电容耦合到 公共电源总线，用于通过公共电源总线从电源传输电力信息信号;以及至少一个接收器，电容耦合到公共电力总线，以接收由发射机发送的电力信息信号，并将接收到的功率信息信号提供给 该至少一个节点。 分别耦合在公共电源总线与电源和至少一个节点中的每一个的多个缓冲器为高频和低频电流提供路径间隔。
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