公开(公告)号：US09495168B2

公开(公告)日：2016-11-15

申请号：US14126466

申请日：2013-05-30

Applicant: Intel Corporation

Inventor： Hongbo Rong ,  Cheng Wang ,  Hyunchul Park ,  Youfeng Wu

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/30 ,  G06F9/45

CPC classification number: G06F9/3838 ,  G06F8/434 ,  G06F8/441 ,  G06F8/443 ,  G06F9/30127 ,  G06F9/3017 ,  G06F9/3834 ,  G06F9/384

Abstract: In an embodiment, a system includes a processor including one or more cores and a plurality of alias registers to store memory range information associated with a plurality of operations of a loop. The memory range information references one or more memory locations within a memory. The system also includes register assignment means for assigning each of the alias registers to a corresponding operation of the loop, where the assignments are made according to a rotation schedule, and one of the alias registers is assigned to a first operation in a first iteration of the loop and to a second operation in a subsequent iteration of the loop. The system also includes the memory coupled to the processor. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，系统包括处理器，其包括一个或多个核和多个别名寄存器，用于存储与循环的多个操作相关联的存储器范围信息。 存储器范围信息引用存储器内的一个或多个存储器位置。 该系统还包括寄存器分配装置，用于将每个别名寄存器分配给循环的对应操作，其中根据旋转调度进行分配，并且在第一次迭代中将一个别名寄存器分配给第一操作 循环和循环的后续迭代中的第二操作。 该系统还包括耦合到处理器的存储器。 描述和要求保护其他实施例。

公开(公告)号：US20160092285A1

公开(公告)日：2016-03-31

申请号：US14497157

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Albert Hartono ,  Nalini Vasudevan ,  Sara S. Baghsorkhi ,  Cheng Wang ,  Youfeng Wu

IPC: G06F11/07 ,  G06F3/06

CPC classification number: G06F8/452 ,  G06F9/4552

Abstract: A computer-implemented method for managing loop code in a compiler includes using a conflict detection procedure that detects across-iteration dependency for arrays of single memory addresses to determine whether a potential across-iteration dependency exists for arrays of memory addresses for ranges of memory accessed by the loop code.

Abstract translation: 用于管理编译器中的循环代码的计算机实现的方法包括使用冲突检测过程，其检测单个存储器地址的阵列的跨迭代依赖性，以确定存储器地址范围内的存储器地址的阵列是否存在潜在的跨迭代依赖性 通过循环代码。

公开(公告)号：US20160092223A1

公开(公告)日：2016-03-31

申请号：US14498178

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Cheng Wang ,  Youfeng Wu ,  Rajesh M Sankaran

IPC: G06F9/30 ,  G06F12/08 ,  G06F9/38

Abstract: A processor of an aspect includes a decode unit to decode a persistent store fence instruction. The processor also includes a memory subsystem module coupled with the decode unit. The memory subsystem module, in response to the persistent store fence instruction, is to ensure that a given data corresponding to the persistent store fence instruction is stored persistently in a persistent storage before data of all subsequent store instructions is stored persistently in the persistent storage. The subsequent store instructions occur after the persistent store fence instruction in original program order. Other processors, methods, systems, and articles of manufacture are also disclosed.

Abstract translation: 一方面的处理器包括解码单元，用于解码持久存储栏指令。 处理器还包括与解码单元耦合的存储器子系统模块。 存储器子系统模块响应于永久存储围栏指令，确保在持久存储指令的数据被持久地存储在永久存储器中之前，与永久存储围栏指令相对应的给定数据被永久地存储在持久存储器中。 随后的存储指令发生在原始程序顺序中的持久存储栏指令之后。 还公开了其它处理器，方法，系统和制品。

公开(公告)号：US10534424B2

公开(公告)日：2020-01-14

申请号：US14986676

申请日：2016-01-02

Applicant: Intel Corporation

Inventor： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

IPC: G06F1/329 ,  G06F1/3287 ,  G06F9/38 ,  G06F9/50 ,  G06F11/34 ,  G06F9/445 ,  G06F9/48

Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

公开(公告)号：US10268497B2

公开(公告)日：2019-04-23

申请号：US14126894

申请日：2013-10-24

Applicant: Intel Corporation

Inventor： Hongbo Rong ,  Hyunchul Park ,  Cheng Wang ,  Youfeng Wu

IPC: G06F9/455 ,  G06F8/41 ,  G06F8/52

Abstract: Methods and apparatus relating to conjugate code generation for efficient dynamic optimizations are described. In an embodiment, a binary code and an intermediate representation (IR) code are generated based at least partially on a source program. The binary code and the intermediate code are transmitted to a virtual machine logic. The binary code and the IR code each include a plurality of regions that are in one-to-one correspondence. Other embodiments are also claimed and described.

公开(公告)号：US09836316B2

公开(公告)日：2017-12-05

申请号：US13631408

申请日：2012-09-28

Applicant: Intel Corporation

Inventor： Cheng Wang ,  Youfeng Wu

IPC: G06F9/455 ,  G06F9/45 ,  G06F9/00

CPC classification number: G06F9/4552 ,  G06F8/44 ,  G06F9/45516 ,  G06F9/45533 ,  G06F9/45554 ,  Y02D10/26 ,  Y02D10/28

Abstract: Technologies for performing flexible code acceleration on a computing device includes initializing an accelerator virtual device on the computing device. The computing device allocates memory-mapped input and output (I/O) for the accelerator virtual device and also allocates an accelerator virtual device context for a code to be accelerated. The computing device accesses a bytecode of the code to be accelerated and determines whether the bytecode is an operating system-dependent bytecode. If not, the computing device performs hardware acceleration of the bytecode via the memory-mapped I/O using an internal binary translation module. However, if the bytecode is operating system-dependent, the computing device performs software acceleration of the bytecode.

公开(公告)号：US20160179586A1

公开(公告)日：2016-06-23

申请号：US14574300

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Cheng Wang ,  Youfeng Wu ,  Sara S. Baghsorkhi ,  Albert Hartono ,  Robert Valentine

IPC: G06F9/52 ,  G06F12/08

CPC classification number: G06F9/528 ,  G06F8/41 ,  G06F8/4451 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30189 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3859 ,  G06F9/3863 ,  G06F12/0828 ,  G06F12/0875 ,  G06F2212/452

Abstract: Embodiments described herein utilize restricted transactional memory (RTM) instructions to implement speculative compile time optimizations that will be automatically rolled back by hardware in the event of a missed speculation. In one embodiment, a lightweight version of RTM for speculative compiler optimization is described to provide lower operational overhead in comparison to conventional RTM implementations used when performing SLE.

Abstract translation: 本文描述的实施例使用受限制的事务存储器（RTM）指令来实现推测性的编译时间优化，其将在错误的猜测的情况下被硬件自动地回滚。 在一个实施例中，与用于执行SLE的常规RTM实现相比，描述了用于推测性编译器优化的轻量级RTM以提供较低的操作开销。

公开(公告)号：US09146844B2

公开(公告)日：2015-09-29

申请号：US13893238

申请日：2013-05-13

Applicant: INTEL CORPORATION

Inventor： Mauricio Breternitz ,  Youfeng Wu ,  Cheng Wang ,  Edson Borin ,  Shiliang Hu ,  Craig B. Zilles

IPC: G06F11/36 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F8/443 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/466 ,  G06F11/3672 ,  G06F11/3688

Abstract: An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

Abstract translation: 本文描述了用于有条件地提交和/或推测性检查点事务的装置和方法，这可能导致事务的动态调整大小。 在二进制代码的动态优化期间，插入事务以提供存储器排序保护措施，这使得动态优化器能够更积极地优化代码。 并且条件提交可以有效地执行动态优化代码，同时尝试防止事务用尽硬件资源。 虽然投机检查点能够在中止交易后快速有效地恢复。 处理器硬件适于支持事务的动态调整大小，诸如包括识别条件提交指令的解码器，推测性检查点指令或两者。 并且处理器硬件还适于执行响应于解码这样的指令来支持条件提交或推测性检查点的操作。

公开(公告)号：US20220326756A1

公开(公告)日：2022-10-13

申请号：US17852066

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

IPC: G06F1/329 ,  G06F1/3287 ,  G06F9/38 ,  G06F9/50 ,  G06F11/34 ,  G06F9/445 ,  G06F9/48

Abstract: Example methods and apparatus to facilitate dynamic core selection are disclosed. An example apparatus includes a first processor core of a first type; a second processor core of a second type different from the first type; and software to: access a user-supplied hint indicative of a user preference to execute program code on the first processor core, the user-supplied hint including a user-defined attribute of the program code; monitor performance of the program code on the first processor core; determine, based on the user-defined attribute of the program code, a predicted performance of the program code on the second processor core is better than the performance of the program code on the first processor core; and ignore the user preference by migrating the program code from the first processor core for execution on the second processor core

公开(公告)号：US10437318B2

公开(公告)日：2019-10-08

申请号：US14986677

申请日：2016-01-02

Applicant: Intel Corporation

Inventor： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

IPC: G06F1/329 ,  G06F1/3287 ,  G06F9/38 ,  G06F9/50 ,  G06F11/34 ,  G06F9/445 ,  G06F9/48

Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.