公开(公告)号：US20220415892A1

公开(公告)日：2022-12-29

申请号：US17358073

申请日：2021-06-25

Applicant: INTEL CORPORATION

Inventor： Wilfred Gomes ,  Abhishek A. Sharma ,  Conor P. Puls ,  Mauro J. Kobrinsky ,  Kevin J. Fischer ,  Derchang Kau ,  Albert Fazio ,  Tahir Ghani

IPC: H01L27/105

Abstract: Integrated circuit (IC) devices with stacked two-level backend memory, and associated systems and methods, are disclosed. An example IC device includes a front end of line (FEOL) layer, including frontend transistors, and a back end of line (BEOL) layer above the FEOL layer. The BEOL layer includes a first memory layer with memory cells of a first type, and a second memory layer with memory cells of a second type. The first memory layer may be between the FEOL layer and the second memory layer, thus forming stacked backend memory. Stacked backend memory architecture may allow significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density. Implementing two different types of backend memory may advantageously increase functionality and performance of backend memory.

公开(公告)号：US20250142948A1

公开(公告)日：2025-05-01

申请号：US18498318

申请日：2023-10-31

Applicant: Intel Corporation

Inventor： Robin Chao ,  Chiao-Ti Huang ,  Guowei Xu ,  Yang Zhang ,  Ting-Hsiang Hung ,  Tao Chu ,  Feng Zhang ,  Chia-Ching Lin ,  Anand S. Murthy ,  Conor P. Puls ,  Kan Zhang

IPC: H01L27/088 ,  H01L23/498 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: An IC device with one or more transistors may also include one or more vias and jumpers for delivering power to the transistors. For instance, a via may be coupled to a power plane. A jumper may be connected to the via and an electrode of a transistor. With the via and jumper, an electrical connection is built between the power plane and the electrode. The via may be self-aligned. The IC device may include a dielectric structure at a first side of the via. A portion of the jumper may be at a second side of the via. The second side opposes the first side. The dielectric structure and the portion of the jumper may be over another dielectric structure that has a different dielectric material from the dielectric structure. The via may be insulated from another electrode of the transistor, which may be coupled to a ground plane.

公开(公告)号：US20250140748A1

公开(公告)日：2025-05-01

申请号：US18498519

申请日：2023-10-31

Applicant: Intel Corporation

Inventor： Payam Amin ,  Mandip Sibakoti ,  Bozidar Marinkovic ,  Tofizur RAHMAN ,  Conor P. Puls

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498

Abstract: A fabrication method and associated integrated circuit (IC) structures and devices that include one or more conductive vias is described herein. In one example, a conductive via is formed from one side of the integrated circuit, and then a portion of the conductive via is widened from a second side of the IC structure opposite the first side. In one example, a resulting IC structure includes a first portion having a first width, a second portion having a second width, and a third portion having a third width, wherein the third portion is between the first portion and the second portion, and the third width is smaller than the first width and the second width. In one such example, the conductive via tapers from both ends towards the third portion between the ends.

公开(公告)号：US20250132245A1

公开(公告)日：2025-04-24

申请号：US18491111

申请日：2023-10-20

Applicant: Intel Corporation

Inventor： Tofizur RAHMAN ,  Conor P. Puls ,  Payam Amin ,  Santhosh Koduri ,  Clay Mortensen ,  Bozidar Marinkovic ,  Shivani Falgun Patel ,  Richard Bonsu ,  Jaladhi Mehta ,  Dincer Unluer

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A fabrication method and associated integrated circuit (IC) structures and devices that include one or more self-insulated vias is described herein. In one example, an IC structure includes a via surrounded by an insulator material and a layer of insulator material between a conductive material of the via and the surrounding insulator material. In one example, the layer of insulator material has one or more material properties that are different than the surrounding insulator material, including one or more of a different density, a different dielectric constant, and a different material composition.

公开(公告)号：US20210407932A1

公开(公告)日：2021-12-30

申请号：US16914045

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Mohammad Kabir ,  Conor P. Puls ,  Babita Dhayal ,  Han Li ,  Keith E. Zawadzki ,  Hannes Greve ,  Avyaya Jayanthinarasimham ,  Mukund Bapna ,  Doug B. Ingerly

IPC: H01L23/00 ,  H01L27/12 ,  H01L23/58 ,  H01L21/762

Abstract: Moisture hermetic guard ring structures for semiconductor devices, related systems, and methods of fabrication are disclosed. Such devices systems, and methods include a guard ring structure laterally surrounding semiconductor devices of a device layer and metal interconnects of an interconnect layer, the guard ring structure extending through the interconnect layer, the device layer, and a bonding layer adjacent one of the interconnect layer or the device layer the bonding layer, and contacting a support substrate coupled to the bonding layer. Such devices systems, and methods may further include via structures having the same material system as the guard ring structure and also extending through the interconnect, the device, and bonding layers and contacting a support substrate.