公开(公告)号：US20240321859A1

公开(公告)日：2024-09-26

申请号：US18187782

申请日：2023-03-22

Applicant: Intel Corporation

Inventor： Tao Chu ,  Minwoo Jang ,  Yanbin Luo ,  Paul Packan ,  Guowei Xu ,  Chiao-Ti Huang ,  Robin Chao ,  Feng Zhang ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L27/02 ,  H01L27/088

CPC classification number: H01L27/0207 ,  H01L27/088

Abstract: An IC device may include an array of transistors. The transistors may have separate gate electrodes. A gate electrode may include polysilicon. The gate electrodes may be separated from each other by one or more electrical insulators. The separated gate electrodes have shorter lengths, compared with connected gate electrodes, which can optimize the performance of the IC device due to local layout effect. Also, the IC device may include conductive structures crossing the support structures of multiple transistors. Such conductive structures may cause strain in the IC device, which can boost the local layout effect. The conductive structures may be insulated from a power plane. Alternatively or additionally, the IC device may include dielectric structures, which may be formed by removing gate electrodes in some of the transistors and providing a dielectric material into the openings. The presence of the dielectric structures can further boost the local layout effect.

公开(公告)号：US20240304621A1

公开(公告)日：2024-09-12

申请号：US18181598

申请日：2023-03-10

Applicant: Intel Corporation

Inventor： Chiao-Ti Huang ,  Tao Chu ,  Robin Chao ,  Guowei Xu ,  Feng Zhang ,  Biswajeet Guha ,  Stephen M. Cea

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Fabrication method for nanoribbon-based transistors and associated transistor arrangements, IC structures, and devices are disclosed. An example fabrication method is based on patterning a foundation over which a superlattice is provided so that a single superlattice may be used to form both PMOS and NMOS stacks of nanoribbons. An example IC structure includes a support, an NMOS stack of nanoribbons stacked vertically above one another over the support, and a PMOS stack of nanoribbons stacked vertically above one another over the support, wherein at least one of the nanoribbons of the NMOS stack is vertically offset with respect to at least one of the nanoribbons of the PMOS stack.

公开(公告)号：US20240290835A1

公开(公告)日：2024-08-29

申请号：US18174007

申请日：2023-02-24

Applicant: Intel Corporation

Inventor： Chiao-Ti Huang ,  Guowei Xu ,  Tao Chu ,  Robin Chao ,  Jaladhi Mehta ,  Brian Greene ,  Chung-Hsun Lin

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/78696

Abstract: Fabrication methods that employ an etch stop layer to assist subfin removal during fabrication of nanoribbon-based transistors are disclosed. An example fabrication method includes providing a stack of nanoribbons above a subfin, where the nanoribbons and the subfin include one or more semiconductor materials; depositing an etch stop layer over a top of the subfin and around portions of the nanoribbons; removing the etch stop layer from around the portions of the nanoribbons; providing a gate dielectric material around the portions of the nanoribbons and over the etch stop layer over the top of the subfin; depositing a gate electrode material around the portions of the nanoribbons; and performing an etch to remove the subfin without substantially removing the etch stop layer.

公开(公告)号：US20240105718A1

公开(公告)日：2024-03-28

申请号：US17934251

申请日：2022-09-22

Applicant: Intel Corporation

Inventor： Tao Chu ,  Guowei Xu ,  Minwoo Jang ,  Yanbin Luo ,  Feng Zhang ,  Ting-Hsiang Hung ,  Chia-Ching Lin

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L27/0886 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/778 ,  H01L29/78696

Abstract: Methods for fabricating an integrated circuit (IC) device with a protection liner between doped semiconductor regions are provided. An example IC device includes a channel material having a first face and a second face opposite the first face, a first doped region and a second doped region in the channel material, extending from the second face towards the first face by a first distance; and an insulator structure in a portion of the channel material between the first and second doped regions, the insulator structure extending from the second face towards the first face by a second distance greater than the first distance. The insulator structure includes a first portion between the second face and the first distance and a second portion between first distance and the second distance. The insulator structure includes a liner material on sidewalls of the first portion but absent on sidewalls of the second portion.

公开(公告)号：US20250107156A1

公开(公告)日：2025-03-27

申请号：US18471710

申请日：2023-09-21

Applicant: Intel Corporation

Inventor： Chiao-Ti Huang ,  Robin Chao ,  Jaladhi Mehta ,  Tao Chu ,  Guowei Xu ,  Ting-Hsiang Hung ,  Feng Zhang ,  Yang Zhang ,  Chia-Ching Lin ,  Chung-Hsun Lin ,  Anand Murthy

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

Abstract: Techniques are provided herein to form an integrated circuit having dielectric material formed in cavities beneath source or drain regions. The cavities may be formed within subfin portions of semiconductor devices. In one such example, a FET (field effect transistor) includes a gate structure extending around a fin or any number of nanowires of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure extends over the semiconductor material in a second direction substantially orthogonal to the first direction. A dielectric fill may be formed in a recess beneath the source or drain regions, or a dielectric liner may be formed on sidewalls of the recess, to prevent epitaxial growth of the source or drain regions from the subfins. Removal of the semiconductor subfin from the backside may then be performed without causing damage to the source or drain regions.

公开(公告)号：US20250089310A1

公开(公告)日：2025-03-13

申请号：US18466246

申请日：2023-09-13

Applicant: Intel Corporation

Inventor： Ting-Hsiang Hung ,  Yang Zhang ,  Robin Chao ,  Guowei Xu ,  Tao Chu ,  Chiao-Ti Huang ,  Feng Zhang ,  Chia-Ching Lin ,  Anand Murthy

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

Abstract: Techniques are provided to form semiconductor devices that include through-gate structures (e.g., gate cut structures or conductive via structures) that have an airgap spacer between the structure and the adjacent gate electrode. In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region) that extends from a first source or drain region to a second source or drain region. A through-gate structure may extend in a third direction through an entire thickness of the gate structure and adjacent to the semiconductor region along the second direction. The through-gate structure may be a dielectric structure (e.g., a gate cut) or a conductive structure (e.g., a via). In either case, an airgap spacer exists between the through-gate structure and the gate structure.

公开(公告)号：US20240321987A1

公开(公告)日：2024-09-26

申请号：US18187990

申请日：2023-03-22

Applicant: Intel Corporation

Inventor： Tao Chu ,  Guowei Xu ,  Robin Chao ,  Chiao-Ti Huang ,  Feng Zhang ,  Minwoo Jang ,  Chia-Ching Lin ,  Biswajeet Guha ,  Yue Zhong ,  Anand S. Murthy

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Described herein are integrated circuit devices that include both nanoribbon-based transistors and fin-shaped transistors. The nanoribbon transistors may have shorter channel lengths than the fin transistors. In addition, the nanoribbon transistors may have thinner gate dielectrics than the fin transistors.