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公开(公告)号：US11991025B2
公开(公告)日：2024-05-21
申请号：US17110228
申请日：2020-12-02
Applicant: Intel Corporation
Inventor： Itamar Levin , Tali Warshavsky
CPC classification number: H04L25/03019 , G06F13/4282 , H04L2025/03636
Abstract: Examples described herein include setting an equalizer tap setting and gain setting in a serializer/deserializer (SerDes). In some examples, determining an equalizer setting and gain setting occurs by causing a mean-square error cost scheme tracking to lock to an offset from a minimum of a cost of the mean-square error cost scheme without pausing error cost tracking. In some examples, the mean-square error cost scheme comprises a least mean square (LMS) scheme. In some examples, determining an equalizer setting comprises: applying increases or decreases to an equalizer setting, and an increase to an equalizer setting can be a different amount than an amount of decrease to an equalizer setting.
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公开(公告)号：US11190208B2
公开(公告)日：2021-11-30
申请号：US16905200
申请日：2020-06-18
Applicant: Intel Corporation
Inventor： Adee Ofir Ran , Amir Mezer , Alon Meisler , Assaf Benhamou , Itamar Levin , Yoni Landau
Abstract: Computing devices and techniques for providing link partner health reporting are described. In one embodiment, for example, an apparatus may include at least one memory, and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a plurality of error counters, each of the plurality of error counters associated with a number of errors, determine the number of errors for each data unit of a plurality of data units associated with a data block, increment each of the plurality of error counters corresponding with the number of errors for each data unit of the plurality of data units, provide a plurality of error counts for the data block to a link partner, the plurality of error counts corresponding to the number of errors accumulated in each of the plurality of error counters for the data block, and reset the plurality of error counters. Other embodiments are described and claimed.
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公开(公告)号：US09917685B2
公开(公告)日：2018-03-13
申请号：US15614470
申请日：2017-06-05
Applicant: Intel Corporation
Inventor： Dima Hammad , Vadim Levin , Amir Laufer , Ron Bar-Lev , Noam Familia , Itamar Levin
CPC classification number: H04L7/0054 , H03L7/0807 , H03L7/093 , H03L7/1075 , H04L1/00 , H04L1/203 , H04L1/24 , H04L7/0016 , H04L7/0062 , H04L7/0079
Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.
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公开(公告)号：US09473259B2
公开(公告)日：2016-10-18
申请号：US14550822
申请日：2014-11-21
Applicant: INTEL CORPORATION
Inventor： Itamar Levin , Kevan A. Lillie , Dima Hammed , Elior Segev , Mingming Xu , Tomer Fael
CPC classification number: H04B17/24 , G06F11/221 , H04B17/00 , H04B17/29 , H04L25/03057 , H04L25/03146 , H04L25/03878
Abstract: Various embodiments are generally directed to techniques for testing a receiver incorporated into an IC to receive a bitstream. An apparatus includes a precharge component to set a VGA to output a differential bias voltage; a taps component to set a tap to form a feedback loop that extends from an output of the bit slicer to the input of the bit slicer through a delay circuit and the tap, the tap to output a first differential voltage to the input of the bit slicer to invert a polarity of a sum of differential voltages at the input of the bit slicer to enable oscillation of the bit slicer, the sum generated from at least the differential bias voltage and the first differential voltage; and a capture component coupled to the output of the bit slicer to capture a series of bit values therefrom. Other embodiments are described and claimed.
Abstract translation: 各种实施例通常涉及用于测试结合到IC中以接收比特流的接收机的技术。 一种装置包括：预充电部件，用于设置VGA以输出差分偏置电压; 抽头分量，用于设置抽头以形成反馈环路，该反馈环路通过延迟电路和抽头从位限幅器的输出延伸到位限幅器的输入，该抽头将第一差分电压输出到位的输入端 切片器，以在位限幅器的输入处反转差分电压之和的极性，以使得位限幅器的振荡，至少从差分偏置电压和第一差分电压产生的和; 以及耦合到所述位限幅器的输出以从其捕获一系列位值的捕获元件。 描述和要求保护其他实施例。
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公开(公告)号：US09215061B2
公开(公告)日：2015-12-15
申请号：US14667146
申请日：2015-03-24
Applicant: Intel Corporation
Inventor： Dima Hammad , Vadim Levin , Amir Laufer , Ron Bar-Lev , Noam Familia , Itamar Levin
CPC classification number: H04L7/0054 , H03L7/0807 , H03L7/093 , H03L7/1075 , H04L1/00 , H04L1/203 , H04L1/24 , H04L7/0016 , H04L7/0062 , H04L7/0079
Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.
Abstract translation: 通常，本公开描述了通信系统中的眼宽测量和边缘化。 一种装置可以被配置为：响应于将边缘化时钟信号同步到接收机时钟信号，将相位检测器与被测接收机的CDR环路滤波器分离; 对环路滤波器施加裕度输入，边缘输入被配置为将边缘化时钟信号的频率移动与边界输入相关的恒定量; 比较第一比特流和第二比特流，并配置为检测与发送的比特流相关的第一比特流的错误; 以及接收机时钟信号或边缘时钟信号的计数周期，其中与被测接收机相关联的眼睛宽度与边缘输入，接收机时钟信号的频率以及当检测到错误时的时钟周期的计数有关。
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Patent Agency Ranking
公开(公告)号：US12261724B2
公开(公告)日：2025-03-25
申请号：US17484205
申请日：2021-09-24
Applicant: Intel Corporation
Inventor： Itamar Levin , Tali Warshavsky
Abstract: An Automatic Gain Control (AGC) SERDES circuit may be used to provide improved gain control for SERDES operation. This AGC SERDES circuit uses an initial gain convergence to determine and store an initial gain level. Once the initial gain convergence is complete, the AGC SERDES circuit uses a signal peak tracking to reduce or prevent saturation events. By setting the gain target based on tracked changes in the equalizer coefficients, the AGC SERDES circuit adapts the gain target to reduce or prevent saturation events and provide the improved communication throughput. A SERDES receiver circuit also provides improved performance using an improved convergence flow within its subcomponent blocks. The improved convergence flow also provides the ability to track environmental changes, voltage changes, and changes to input parameters, and can be performed while data is running on the link to provide continuously improved communication channel performance.
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公开(公告)号：US20230198631A1
公开(公告)日：2023-06-22
申请号：US17556696
申请日：2021-12-20
Applicant: Intel Corporation
Inventor： Itamar Levin , Adee Ofir Ran
CPC classification number: H04B10/6971 , H04B10/6932 , H04B10/614 , H04B10/503
Abstract: Sampling circuitry for receiving an analog signal from photodetector circuitry and generating a sample analog signal. Equalization circuitry for generating an equalized signal comprising first and second sample values corresponding with a cursor tap and a first postcursor tap, and one or more third sample values corresponding with taps other than the cursor tap and the first postcursor tap. In the equalized signal, amplitudes of the first and second sample values are substantially equal while the third sample values are attenuated relative to the first and second sample values. The first and second sample values correspond with two or more first symbols of a first alphabet. Data slicer and modulo circuitry to generate a data signal based on the equalized signal and perform a modulo operation on the two or more first symbols and to generate one or more second symbols. The second symbols are according to a second alphabet.
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公开(公告)号：US20230099103A1
公开(公告)日：2023-03-30
申请号：US17484105
申请日：2021-09-24
Applicant: Intel Corporation
Inventor： Itamar Levin , Tali Warshavsky , Yekutiel Uliel
Abstract: A CTLE-based SERDES receiver circuit using ISI metering provides an improved SERDES I/O performance. The CTLE SERDES receiver circuit may include an analog receiver frontend to generate an analog-to-digital converter (ADC) digital signal and a reduced ISI signal, a data path circuit to generate a sliced data stream and sliced cursor error stream, a digital signal processing (DSP) circuit to generate a converged data stream, a multi-tap intersymbol interference (ISI) assessment circuit to generate a weighted ISI sum, and an ISI minimization circuit to generate a continuous time linear equalizer (CTLE) adaptation control signal based on the weighted ISI sum.
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公开(公告)号：US11356306B2
公开(公告)日：2022-06-07
申请号：US15941071
申请日：2018-03-30
Applicant: Intel Corporation
Inventor： Nishantkumar Shah , Kevan A. Lillie , Adee Ofir Ran , Itamar Levin , Kent Lusted
Abstract: Technologies for cooperative link equalization include a network device with a network interface controller (NIC). The NIC is to monitor variation in a property of a link channel that connects the network device with a target network device. The NIC detects, based on the channel variation, an event that triggers a condition to change an equalization setting of the link channel. In response to the detection, the NIC communicates, via an in-band equalization control channel, changes to the equalization setting of the link channel to the target network device.
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公开(公告)号：US09680668B2
公开(公告)日：2017-06-13
申请号：US14572756
申请日：2014-12-16
Applicant: Intel Corporation
Inventor： Amir Laufer , Itamar Levin
CPC classification number: H04L25/03057 , H04L25/03885 , H04L2025/03579
Abstract: Described is an apparatus which comprises a decision feedback equalizer (DFE) having a first DFE tap path and non-first DFE tap paths, wherein the DFE includes a variable delay circuit in a signal path of the non-first DFE tap paths. In some embodiment, an apparatus is provided which comprises: a summer; a slicer to receive input from the summer; a first feedback loop to cancel a first post-cursor, the first feedback loop forming a loop by coupling the slicer to the summer; and a second feedback loop to cancel a second post-cursor, the second feedback loop forming a loop by coupling an input of the first feedback loop to the summer, wherein the second feedback loop having a programmable delay at its input.
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