公开(公告)号：US20190042127A1

公开(公告)日：2019-02-07

申请号：US15868627

申请日：2018-01-11

Applicant: Intel Corporation

Inventor： Scott J. Weber ,  David Greenhill ,  Sean R. Atsatt ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu ,  Jun Pin Tan

IPC: G06F3/06 ,  G06F12/0802

Abstract: An integrated circuit device may cache configuration data to enable rapid configuration from fabric cache memory. The integrated circuit device may include programmable logic fabric having configuration memory and programmable logic elements controlled by the configuration memory, and sector-aligned memory apart from the programmable logic fabric. A first sector of the configuration memory may be programmed with first configuration data. The sector-aligned memory may include a first sector of sector-aligned memory that may cache the first configuration data while the configuration memory is programmed with the first configuration data a first time. A second sector of sector-aligned memory may cache second configuration data for a second sector of the configuration memory in parallel while the first sector of sector-aligned memory caches the first configuration data for the first sector of the configuration memory.

公开(公告)号：US10666265B2

公开(公告)日：2020-05-26

申请号：US16146849

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  James Ball ,  Simon Chong ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu ,  Jun Pin Tan

IPC: H03K19/173 ,  G06F7/38 ,  H03K19/1776 ,  H03K19/17768 ,  H03K19/17704 ,  H03K19/17758

Abstract: An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die and having configuration memory. The integrated circuit device may also include a base die that may provide memory and/or operating supporting circuitry. The first die and the second die may be coupled using a high-speed parallel interface. The interface may employ microbumps. The first die and the second die may also include controllers for the interface.

公开(公告)号：US20190043536A1

公开(公告)日：2019-02-07

申请号：US15868304

申请日：2018-01-11

Applicant: Intel Corporation

Inventor： Scott J. Weber ,  Sean R. Atsatt ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu ,  Jun Pin Tan

IPC: G11C5/02 ,  G11C5/06 ,  H03K19/177

Abstract: An integrated circuit device may include programmable logic fabric on a first integrated circuit die and sector-aligned memory on a second integrated circuit die to enable large amounts of data to be rapidly processed by a sector of programmable logic of the programmable logic device. The programmable logic fabric may include a first and second sectors. The first sector may be programmed with a circuit design that operates on a first set of data. The sector-aligned memory may include a first sector of sector-aligned memory directly accessible by the first sector of programmable logic fabric and a second sector of sector-aligned memory directly accessible by the second sector of programmable logic fabric. The first sector of sector-aligned memory may store the first set of data.

公开(公告)号：US20180143860A1

公开(公告)日：2018-05-24

申请号：US15358665

申请日：2016-11-22

Applicant: Intel Corporation

Inventor： Aravind Dasu ,  Scott Weber ,  Jun Pin Tan ,  Arifur Rahman

IPC: G06F9/50 ,  G06F9/48

CPC classification number: G06F9/5027 ,  G06F9/46 ,  G06F9/4843 ,  G06F15/7867 ,  G06F15/7889 ,  G11C5/02 ,  Y02D10/12 ,  Y02D10/13

Abstract: A host processor may utilize a coprocessor to accelerate the performance of a task. Upon receiving a acceleration request from the host processor, the coprocessor may identify and select an available logic sector within the coprocessor that can be used to perform a task associated with the acceleration request. In some cases, the selected logic sector may not be configured to perform the task, in which case the selected logic sector may be reconfigured. The configuration bit stream used to reconfigure the selected logic sector to perform the task may be retrieved from a stacked memory die mounted on the coprocessor, or, if the configuration bit stream is not stored in the stacked memory die, the configuration bit stream may be retrieved from an external memory through the host processor. Load balancing may be performed to dynamically allocate additional logic sectors to time-critical tasks.

公开(公告)号：US20180143777A1

公开(公告)日：2018-05-24

申请号：US15358738

申请日：2016-11-22

Applicant: Intel Corporation

Inventor： Aravind Dasu ,  Scott Weber ,  Jun Pin Tan ,  Arifur Rahman

IPC: G06F3/06 ,  G11C5/02 ,  G11C5/06

CPC classification number: G06F3/0629 ,  G06F3/061 ,  G06F3/0647 ,  G06F3/0673 ,  G06F15/7871 ,  G11C5/02 ,  G11C5/06 ,  Y02D10/12 ,  Y02D10/13

Abstract: A system may include a host processor, a coprocessor for accelerating tasks received from the host processor, and one or more memory dies mounted to the coprocessor. The coprocessor and the memory die may be part of an integrated circuit package. The memory die may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor over through-silicon vias. Each logic sector may include one or more data registers that are loaded with configuration data from the memory die. Multiple data registers may be loaded with configuration data simultaneously. The configuration data may be loaded onto an array of configuration memory cells using the data registers. Multiple data registers may be pipelined to allow simultaneous loading of configuration data into multiple sub-arrays of the array of configuration memory cells.

公开(公告)号：US11223361B2

公开(公告)日：2022-01-11

申请号：US16882029

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  James Ball ,  Simon Chong ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu ,  Jun Pin Tan

IPC: H03K19/1776 ,  H03K19/17704 ,  H03K19/17758 ,  H03K19/17768

Abstract: An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die and having configuration memory. The integrated circuit device may also include a base die that may provide memory and/or operating supporting circuitry. The first die and the second die may be coupled using a high-speed parallel interface. The interface may employ microbumps. The first die and the second die may also include controllers for the interface.