公开(公告)号：US09916253B2

公开(公告)日：2018-03-13

申请号：US14173602

申请日：2014-02-05

Applicant: Intel Corporation

Inventor： Karthikeyan Avudaiyappan ,  Sourabh Alurkar

IPC: G06F13/00 ,  G06F12/0895

CPC classification number: G06F12/0895

Abstract: A method for supporting a plurality of requests for access to a data cache memory (“cache”) is disclosed. The method comprises accessing a first set of requests to access the cache, wherein the cache comprises a plurality of blocks. Further, responsive to the first set of requests to access the cache, the method comprises accessing a tag memory that maintains a plurality of copies of tags for each entry in the cache and identifying tags that correspond to individual requests of the first set. The method also comprises performing arbitration in a same clock cycle as the accessing and identifying of tags, wherein the arbitration comprises: (a) identifying a second set of requests to access the cache from the first set, wherein the second set accesses a same block within the cache; and (b) selecting each request from the second set to receive data from the same block.

公开(公告)号：US20180024940A1

公开(公告)日：2018-01-25

申请号：US15678057

申请日：2017-08-15

Applicant: Intel Corporation

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/1027 ,  G06F12/0875 ,  G06F12/1045 ,  G06F12/0802

CPC classification number: G06F12/1027 ,  G06F12/0802 ,  G06F12/0875 ,  G06F12/1054 ,  G06F12/1063 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/152 ,  G06F2212/608 ,  G06F2212/651 ,  G06F2212/652 ,  G06F2212/657 ,  G06F2212/681 ,  G06F2212/684

Abstract: Systems and methods for accessing a unified translation lookaside buffer (TLB) are disclosed. A method includes receiving an indicator of a level one translation lookaside buffer (L1TLB) miss corresponding to a request for a virtual address to physical address translation, searching a cache that includes virtual addresses and page sizes that correspond to translation table entries (TTEs) that have been evicted from the L1TLB, where a page size is identified, and searching a second level TLB and identifying a physical address that is contained in the second level TLB. Access is provided to the identified physical address.

公开(公告)号：US09858206B2

公开(公告)日：2018-01-02

申请号：US15353053

申请日：2016-11-16

Applicant: Intel Corporation

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/12 ,  G06F12/08 ,  G06F12/128 ,  G06F12/0808 ,  G06F12/0811

CPC classification number: G06F12/128 ,  G06F12/0802 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/126 ,  G06F2212/283 ,  G06F2212/608 ,  G06F2212/70

Abstract: Systems and methods for flushing a cache with modified data are disclosed. Responsive to a request to flush data from a cache with modified data to a next level cache that does not include the cache with modified data, the cache with modified data is accessed using an index and a way and an address associated with the index and the way is secured. Using the address, the cache with modified data is accessed a second time and an entry that is associated with the address is retrieved from the cache with modified data. The entry is placed into a location of the next level cache.

公开(公告)号：US09678882B2

公开(公告)日：2017-06-13

申请号：US13649532

申请日：2012-10-11

Applicant: Intel Corporation

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/00 ,  G06F12/0891 ,  G06F12/0811

CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0837 ,  G06F12/0897 ,  G06F2212/1024

Abstract: Systems and methods for non-blocking implementation of cache flush instructions are disclosed. As a part of a method, data is accessed that is received in a write-back data holding buffer from a cache flushing operation, the data is flagged with a processor identifier and a serialization flag, and responsive to the flagging, the cache is notified that the cache flush is completed. Subsequent to the notifying, access is provided to data then present in the write-back data holding buffer to determine if data then present in the write-back data holding buffer is flagged.

公开(公告)号：US09632947B2

公开(公告)日：2017-04-25

申请号：US13970277

申请日：2013-08-19

Applicant: Intel Corporation

Inventor： Karthikeyan Avudaiyappan ,  Paul G. Chan

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/0897 ,  G06F12/0855

CPC classification number: G06F12/0897 ,  G06F9/3867 ,  G06F12/0859 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0875 ,  G06F2212/452 ,  G06F2212/60

Abstract: A method for acquiring cache line data associated with a load from respective hierarchical cache data storage components. As a part of the method, a store queue is accessed for one or more portions of a cache line associated with a load, and, if the one or more portions of the cache line is held in the store queue, the one or more portions of the cache line is stored in a load queue location associated with the load. The load is completed if the one or more portions of the cache line stored in the load queue location includes all portions of the cache line associated with the load.

公开(公告)号：US10565113B2

公开(公告)日：2020-02-18

申请号：US14825502

申请日：2015-08-13

Applicant: Intel Corporation

Inventor： Karthikeyan Avudaiyappan

IPC: G06F12/0831 ,  G06F12/1045 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/0855

Abstract: Methods and systems for managing synonyms in VIPT caches are disclosed. A method includes tracking lines of a copied cache using a directory, examining a specified bit of a virtual address that is associated with a load request and determining its status and making an entry in one of a plurality of parts of the directory based on the status of the specified bit of the virtual address that is examined. The method further includes updating one of, and invalidating the other of, a cache line that is associated with the virtual address that is stored in a first index of the copied cache, and a cache line that is associated with a synonym of the virtual address that is stored at a second index of the copied cache, upon receiving a request to update a physical address associated with the virtual address.

公开(公告)号：US10346302B2

公开(公告)日：2019-07-09

申请号：US15654481

申请日：2017-07-19

Applicant: Intel Corporation

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/12 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0897

Abstract: A method for maintaining the coherency of a store coalescing cache and a load cache is disclosed. As a part of the method, responsive to a write-back of an entry from a level one store coalescing cache to a level two cache, the entry is written into the level two cache and into the level one load cache. The writing of the entry into the level two cache and into the level one load cache is executed at the speed of access of the level two cache.

公开(公告)号：US10310987B2

公开(公告)日：2019-06-04

申请号：US15678057

申请日：2017-08-15

Applicant: Intel Corporation

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/00 ,  G06F12/1027 ,  G06F12/0802 ,  G06F12/1045 ,  G06F12/0875

Abstract: Systems and methods for accessing a unified translation lookaside buffer (TLB) are disclosed. A method includes receiving an indicator of a level one translation lookaside buffer (L1TLB) miss corresponding to a request for a virtual address to physical address translation, searching a cache that includes virtual addresses and page sizes that correspond to translation table entries (TTEs) that have been evicted from the L1TLB, where a page size is identified, and searching a second level TLB and identifying a physical address that is contained in the second level TLB. Access is provided to the identified physical address.

公开(公告)号：US10255187B2

公开(公告)日：2019-04-09

申请号：US15145615

申请日：2016-05-03

Applicant: Intel Corporation

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/00 ,  G06F12/0862 ,  G06F12/02 ,  G06F9/00 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38

Abstract: A method for weak stream software data and instruction prefetching using a hardware data prefetcher is disclosed. A method includes, determining if software includes software prefetch instructions, using a hardware data prefetcher, and, accessing the software prefetch instructions if the software includes software prefetch instructions. Using the hardware data prefetcher, weak stream software data and instruction prefetching operations are executed based on the software prefetch instructions, free of training operations.

公开(公告)号：US10248570B2

公开(公告)日：2019-04-02

申请号：US15862496

申请日：2018-01-04

Applicant: Intel Corporation

Inventor： Mohammad Abdallah ,  Ravishankar Rao ,  Karthikeyan Avudaiyappan

IPC: G06F13/00 ,  G06F3/00 ,  G06F13/12 ,  G06F12/00 ,  G06F15/00 ,  G06F12/0864 ,  G06F12/0862 ,  G06F12/0811 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897

Abstract: A method for predicting a way of a set associative shadow cache is disclosed. As a part of a method, a request to fetch a first far taken branch instruction of a first cache line from an instruction cache is received, and responsive to a hit in the instruction cache, a predicted way is selected from a way array using a way that corresponds to the hit in the instruction cache. A second cache line is selected from a shadow cache using the predicted way and the first cache line and the second cache line are forwarded in the same clock cycle.