公开(公告)号：US20200251159A1

公开(公告)日：2020-08-06

申请号：US16854280

申请日：2020-04-21

Applicant: Intel Corporation

Inventor： Narasimha Lanka ,  Kuljit Bains ,  Lakshmipriya Seshan

IPC: G11C11/4063 ,  H01L27/108 ,  H01L27/06 ,  H01L23/538 ,  G11C5/06

Abstract: An embodiment of a memory apparatus may include a memory core, a plurality of through-silicon vias (TSVs), and data bus inversion logic coupled between the memory core and the TSVs to encode and decode a data signal on a signal path through the TSVs in accordance with a data bus inversion of the data signal. Other embodiments are disclosed and claimed.

公开(公告)号：US12298833B2

公开(公告)日：2025-05-13

申请号：US18007627

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Ujjwal Gupta ,  Ankush Varma ,  Lakshmipriya Seshan ,  Nikethan Shivanand Baligar ,  Nikhil Gupta ,  Swadesh Choudhary ,  Yogesh Bansal

IPC: G06F1/324 ,  G06F1/10 ,  G06F1/3203 ,  G06F11/34 ,  G06F13/00 ,  G06F15/16

Abstract: A single communication fabric for a data processing apparatus is provided. The fabric has an interconnection network to provide a topology of data communication channels between a plurality of data-handling functional units. The interconnection network has a first interconnection domain to provide data communication between a first subset of the data-handling functional units and a second interconnection domain to provide data communication between a second subset of the data-handling functional units. The power management circuitry is arranged to control a first performance level for the first interconnection domain independently from control of a second performance level for the second interconnection domain. Machine readable instructions and a method are provided to concurrently set performance levels of two different fabric domains to respective different operating frequencies.

公开(公告)号：US20240095206A1

公开(公告)日：2024-03-21

申请号：US18525289

申请日：2023-11-30

Applicant: Intel Corporation

Inventor： Sampath Dakshinamurthy ,  Pooja Jadhav ,  Neethumol O.U. ,  Lakshmipriya Seshan

IPC: G06F13/42

CPC classification number: G06F13/4273 ,  G06F2213/0064

Abstract: Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to semiconductor interconnects, such as on-package die-to-die (D2D) interconnects, for example. Specifically, embodiments herein may relate to on-package D2D interconnects for memory that use or relate to the Universal Chiplet Interconnect Express (UCIe) adapter or physical layer (PHY). Other embodiments are described and claimed.

公开(公告)号：US20230258716A1

公开(公告)日：2023-08-17

申请号：US18129315

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Swadesh Choudhary ,  Debendra Das Sharma ,  Gerald Pasdast ,  Zuogo Wu ,  Narasimha Lanka ,  Lakshmipriya Seshan

IPC: G01R31/3183 ,  G01R31/317

CPC classification number: G01R31/318314 ,  G01R31/31712 ,  G01R31/31718

Abstract: Techniques to perform semiconductor testing are described. Test equipment may test a chiplet for compliance with a semiconductor specification. A test device may connect to a test package with a model chiplet and a device under test (DUT) chiplet. The model chiplet may comprise a known good model (KGM) of the semiconductor specification. The test device may use the model chiplet to test the DUT chiplet. Other embodiments are described and claimed.

公开(公告)号：US20220327276A1

公开(公告)日：2022-10-13

申请号：US17844356

申请日：2022-06-20

Applicant: Intel Corporation

Inventor： Lakshmipriya Seshan ,  Gerald Pasdast ,  Peipei Wang ,  Narasimha Lanka ,  Swadesh Choudhary ,  Zuoguo Wu ,  Debendra Das Sharma

IPC: G06F30/398 ,  G06F30/347 ,  G06F30/392

Abstract: In one embodiment, an apparatus includes a first die comprising: a die-to-die adapter to communicate with protocol layer circuitry and physical layer circuitry, where the die-to-die adapter is to receive first information of a first interconnect protocol; and the physical layer circuitry coupled to the die-to-die adapter. The physical layer circuitry is configured to receive and output the first information to a second die via an interconnect and comprises: a first plurality of transmitters to transmit data via a first plurality of data lanes; and at least one redundant transmitter. The physical layer circuitry may be configured to remap a first data lane of the first plurality of data lanes to the at least one redundant transmitter. Other embodiments are described and claimed.

公开(公告)号：US20220318111A1

公开(公告)日：2022-10-06

申请号：US17844348

申请日：2022-06-20

Applicant: Intel Corporation

Inventor： Swadesh Choudhary ,  Narasimha Lanka ,  Debendra Das Sharma ,  Lakshmipriya Seshan ,  Zuoguo Wu ,  Gerald Pasdast

IPC: G06F11/263 ,  G06F13/42

Abstract: In one embodiment, an apparatus comprises a first die that includes: a die-to-die adapter comprising a plurality of first registers, the die-to-die adapter to communicate with protocol layer circuitry via a flit-aware die-to-die interface (FDI) and physical layer circuitry via a raw die-to-die interface (RDI), wherein the die-to-die adapter is to receive message information of a first interconnect protocol; and the physical layer circuitry coupled to the die-to-die adapter, the physical layer circuity comprising a plurality of second registers, where the physical layer circuitry is to receive and output the message information to a second die via an interconnect having a mainband and a sideband. During a test of the apparatus, the sideband is to enable access to information in at least one of the plurality of first registers or at least one of the plurality of second registers. Other embodiments are described and claimed.

公开(公告)号：US20210004347A1

公开(公告)日：2021-01-07

申请号：US17029288

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Narasimha Lanka ,  Lakshmipriya Seshan ,  Gerald S. Pasdast ,  Zuoguo Wu

IPC: G06F13/42 ,  G06F13/40

Abstract: Systems, methods, and apparatuses associated with an approximate majority based data bus inversion technique are disclosed. A method comprises obtaining, at a first device connected by a plurality of lanes to a second device, original data comprising first bits and second bits, where the first bits are to be transmitted in a new clock cycle via first lanes of the plurality of lanes, and the second bits are to be transmitted in the new clock cycle via second lanes of the plurality of lanes. The method further includes determining whether a first criterion associated with the first bits is met, determining whether a second criterion associated with the second bits is met, and transmitting an inverted version of the original data via the plurality of lanes based, at least in part, on determining that the first criterion and the second criterion are met.