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    STANDARD INTERFACES FOR DIE TO DIE (D2D) INTERCONNECT STACKS
    11.
    发明申请
    STANDARD INTERFACES FOR DIE TO DIE (D2D) INTERCONNECT STACKS 有权

    公开(公告)号：US20220327083A1

    公开(公告)日：2022-10-13

    申请号：US17844366

    申请日：2022-06-20

    Applicant: Intel Corporation

    Inventor： Debendra Das Sharma ,  Swadesh Choudhary ,  Narasimha Lanka ,  Zuoguo Wu ,  Gerald Pasdast ,  Lakshmipriya Seshan

    IPC: G06F13/42 ,  H01L23/538 ,  G06F13/40

    Abstract: In one embodiment, a first die comprises: a first die-to-die adapter to communicate with first protocol layer circuitry via a flit-aware die-to-die interface (FDI) and first physical layer circuitry via a raw die-to-die interface (RDI), where the first die-to-die adapter is to receive message information comprising first information of a first interconnect protocol; and the first physical layer circuitry coupled to the first die-to-die adapter. The first physical layer circuitry may be configured to receive and output the first information to a second die via an interconnect, the first physical layer circuitry comprising a plurality of modules, each of the plurality of modules comprising an analog front end having transmitter circuitry and receiver circuitry. Other embodiments are described and claimed.

    PHY-BASED RETRY TECHNIQUES FOR DIE-TO-DIE INTERFACES
    12.
    发明申请
    PHY-BASED RETRY TECHNIQUES FOR DIE-TO-DIE INTERFACES 有权

    公开(公告)号：US20210344354A1

    公开(公告)日：2021-11-04

    申请号：US17359517

    申请日：2021-06-26

    Applicant: Intel Corporation

    Inventor： Narasimha Lanka ,  Lakshmipriya Seshan ,  Debendra Das Sharma ,  Zuoguo Wu ,  Gerald S. Pasdast

    IPC: H03M13/11 ,  H03M13/00

    Abstract: In one embodiment, an apparatus includes PHY circuitry to implement a PHY-based retry technique, e.g., in die-to-die interfaces. The PHY circuitry includes a retry buffer to buffer data provided by the interface controller and error detection code generation circuitry to generate error detection codes based on input data. The PHY circuitry is to implement the retry technique by detecting a stall signal asserted by another apparatus across the channel, causing the error detection code generation circuitry to generate error detection codes based on data in the retry buffer, and transmitting the data from the retry buffer and its corresponding error detection codes across the channel to the other apparatus.

    COMPLIANCE AND DEBUG TESTING OF A DIE-TO-DIE INTERCONNECT
    17.
    发明申请
    COMPLIANCE AND DEBUG TESTING OF A DIE-TO-DIE INTERCONNECT 有权

    公开(公告)号：US20220318111A1

    公开(公告)日：2022-10-06

    申请号：US17844348

    申请日：2022-06-20

    Applicant: Intel Corporation

    Inventor： Swadesh Choudhary ,  Narasimha Lanka ,  Debendra Das Sharma ,  Lakshmipriya Seshan ,  Zuoguo Wu ,  Gerald Pasdast

    IPC: G06F11/263 ,  G06F13/42

    Abstract: In one embodiment, an apparatus comprises a first die that includes: a die-to-die adapter comprising a plurality of first registers, the die-to-die adapter to communicate with protocol layer circuitry via a flit-aware die-to-die interface (FDI) and physical layer circuitry via a raw die-to-die interface (RDI), wherein the die-to-die adapter is to receive message information of a first interconnect protocol; and the physical layer circuitry coupled to the die-to-die adapter, the physical layer circuity comprising a plurality of second registers, where the physical layer circuitry is to receive and output the message information to a second die via an interconnect having a mainband and a sideband. During a test of the apparatus, the sideband is to enable access to information in at least one of the plurality of first registers or at least one of the plurality of second registers. Other embodiments are described and claimed.

    APPROXIMATE DATA BUS INVERSION TECHNIQUE FOR LATENCY SENSITIVE APPLICATIONS
    18.
    发明申请
    APPROXIMATE DATA BUS INVERSION TECHNIQUE FOR LATENCY SENSITIVE APPLICATIONS 有权

    公开(公告)号：US20210004347A1

    公开(公告)日：2021-01-07

    申请号：US17029288

    申请日：2020-09-23

    Applicant: Intel Corporation

    Inventor： Narasimha Lanka ,  Lakshmipriya Seshan ,  Gerald S. Pasdast ,  Zuoguo Wu

    IPC: G06F13/42 ,  G06F13/40

    Abstract: Systems, methods, and apparatuses associated with an approximate majority based data bus inversion technique are disclosed. A method comprises obtaining, at a first device connected by a plurality of lanes to a second device, original data comprising first bits and second bits, where the first bits are to be transmitted in a new clock cycle via first lanes of the plurality of lanes, and the second bits are to be transmitted in the new clock cycle via second lanes of the plurality of lanes. The method further includes determining whether a first criterion associated with the first bits is met, determining whether a second criterion associated with the second bits is met, and transmitting an inverted version of the original data via the plurality of lanes based, at least in part, on determining that the first criterion and the second criterion are met.

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