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    FLOATING POINT MULTIPLY-ACCUMULATE UNIT FOR DEEP LEARNING
    13.
    发明申请
    FLOATING POINT MULTIPLY-ACCUMULATE UNIT FOR DEEP LEARNING 有权

    公开(公告)号：US20220188075A1

    公开(公告)日：2022-06-16

    申请号：US17688131

    申请日：2022-03-07

    Applicant: Intel Corporation

    Inventor： Arnab Raha ,  Mark A. Anders ,  Raymond Jit-Hung Sung ,  Debabrata Mohapatra ,  Deepak Abraham Mathaikutty ,  Ram K. Krishnamurthy ,  Himanshu Kaul

    IPC: G06F7/544 ,  G06F7/483 ,  G06N3/08

    Abstract: A FPMAC operation has two operands: an input operand and a weight operand. The operands may have a format of FP16, BF16, or INT8. Each operand is split into two portions. The two portions are stored in separate storage units. Then operands are transferred to register files of a PE, with each register file storing bits of an operand sequentially. The PE performs the FPMAC operation based on the operands. The PE may include an FPMAC unit configured to compute an individual partial sum of the PE. The PE may also include an FP adder to accumulate the individual partial sum with other data, such as an output from another PE or an output form another PE array. The FP adder may be fused with the FPMAC unit in a single circuit that can do speculative alignment and has separate critical paths for alignment and normalization.

    Fused voltage level shifting latch
    15.
    发明授权
    Fused voltage level shifting latch 有权

    公开(公告)号：US10756736B2

    公开(公告)日：2020-08-25

    申请号：US16335092

    申请日：2017-08-30

    Applicant: Intel Corporation

    Inventor： Steven K. Hsu ,  Amit Agarwal ,  Ram K. Krishnamurthy

    IPC: H03K19/0185 ,  H03K3/037

    Abstract: Some embodiments include apparatus and methods using an input stage and an output stage of a circuit. The input stage operates to receive an input signal and a clock signal and to provide an internal signal at an internal node based at least in part on the input signal. The input signal has levels in a first voltage range. The internal signal has levels in a second voltage range greater than the first voltage range. The output stage operates to receive the internal signal, the clock signal, and an additional signal generated based on the input signal. The output stage provides an output signal based at least in part on the input signal and the additional signal. The output signal has a third voltage range greater than the first voltage range.

    Shared keeper and footer flip-flop
    16.
    发明授权
    Shared keeper and footer flip-flop 有权

    公开(公告)号：US10193536B2

    公开(公告)日：2019-01-29

    申请号：US15860562

    申请日：2018-01-02

    Applicant: INTEL CORPORATION

    Inventor： Amit Agarwal ,  Steven K. Hsu ,  Simeon Realov ,  Iqbal R. Rajwani ,  Ram K. Krishnamurthy

    IPC: H03K3/3562 ,  H03K3/037

    Abstract: An apparatus is provided which comprises: a clock node; a first inverter having an input coupled to the clock node; a data node; a master latch with a shared p-type keeper coupled to an output of the first inverter, the master latch coupled to the data node; and a slave latch coupled to an output of the master latch, the slave latch having a shared p-type keeper and a shared n-type footer, wherein the shared p-type keeper and the shared n-type footer of the slave latch are coupled to the clock node and the input of the first inverter.

    Apparatus and method for low power fully-interruptible latches and master-slave flip-flops
    17.
    发明授权
    Apparatus and method for low power fully-interruptible latches and master-slave flip-flops 有权

    公开(公告)号：US09960753B2

    公开(公告)日：2018-05-01

    申请号：US15209531

    申请日：2016-07-13

    Applicant: Intel Corporation

    Inventor： Steven K. Hsu ,  Amit Agarwal ,  Ram K. Krishnamurthy

    IPC: H03K3/289 ,  H03K3/3562 ,  H03K3/356

    CPC classification number: H03K3/35625 ,  H03K3/356104

    Abstract: Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node. Described is a flip-flop which comprises: a first latch including: a first AOI logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply, the first latch having an output node; and a second latch having an input node coupled to the output node of the first latch, the second latch having an output node to provide an output of the flip-flop.

    Threshold filtering of compressed domain data using steering vector
    18.
    发明授权
    Threshold filtering of compressed domain data using steering vector 有权
    使用导向矢量对压缩域数据进行阈值滤波

    公开(公告)号：US09503747B2

    公开(公告)日：2016-11-22

    申请号：US14607113

    申请日：2015-01-28

    Applicant: Intel Corporation

    Inventor： Sudhir K. Satpathy ,  Sanu K. Mathew ,  Ram K. Krishnamurthy

    IPC: G06F7/544 ,  H04N19/48 ,  G06F7/24 ,  G06T7/00 ,  H04N19/85

    CPC classification number: G06F7/533 ,  G06F7/24 ,  G06F7/5443 ,  G06T7/74 ,  G06T7/97 ,  H04N19/48 ,  H04N19/85

    Abstract: In an embodiment, a processor includes a compression domain threshold filter coupled to a plurality of cores. The compression domain threshold filter is to: receive a sample vector of compressed data to be filtered; calculate, based at least on a first subset of the elements of the sample vector, an estimated upper bound value of a dot product of the sample vector and a steering vector; determine whether the estimated upper bound value of the dot product satisfies a filter threshold value; and in response to a determination that the estimated upper bound value of the dot product does not satisfy the filter threshold value, discard the sample vector without completion of a calculation of the dot product of the sample vector and the steering vector. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括耦合到多个核的压缩域阈值滤波器。 压缩域阈值滤波器是：接收要滤波的压缩数据的采样向量; 至少基于样本矢量的元素的第一子集计算样本矢量和导向矢量的点积的估计上限值; 确定点积的估计上限值是否满足滤波器阈值; 并且响应于确定点积的估计上限值不满足滤波器阈值，而不完成样本矢量和导向矢量的点乘积的计算而丢弃样本矢量。 描述和要求保护其他实施例。

    Apparatus and method for low power fully-interruptible latches and master-slave flip-flops
    19.
    发明授权
    Apparatus and method for low power fully-interruptible latches and master-slave flip-flops 有权
    低功耗全中断锁存器和主从触发器的装置和方法

    公开(公告)号：US09035686B1

    公开(公告)日：2015-05-19

    申请号：US14069198

    申请日：2013-10-31

    Applicant: Intel Corporation

    Inventor： Steven K. Hsu ,  Amit Agarwal ,  Ram K. Krishnamurthy

    IPC: H03K3/356 ,  H03K3/037

    CPC classification number: H03K3/35625 ,  H03K3/356104

    Abstract: Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node. Described is a flip-flop which comprises: a first latch including: a first AOI logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply, the first latch having an output node; and a second latch having an input node coupled to the output node of the first latch, the second latch having an output node to provide an output of the flip-flop.

    Abstract translation: 描述了一种锁存器，其包括：第一AND-OR反相（AOI）逻辑门; 以及耦合到所述第一AOI逻辑门的第二AOI逻辑门，其中所述第一和第二AOI逻辑门具有耦合到电源节点的相应的第一和第二保持器装置。 描述了一种触发器，其包括：第一锁存器，包括：第一AOI逻辑门; 以及耦合到所述第一AOI逻辑门的第二AOI逻辑门，其中所述第一和第二AOI逻辑门具有耦合到电源的相应的第一和第二保持器装置，所述第一锁存器具有输出节点; 以及第二锁存器，其具有耦合到所述第一锁存器的输出节点的输入节点，所述第二锁存器具有输出节点以提供所述触发器的输出。

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