公开(公告)号：US10199353B2

公开(公告)日：2019-02-05

申请号：US15262935

申请日：2016-09-12

Applicant: INTEL CORPORATION

Inventor： Navneet K. Singh ,  Ranjul Balakrishnan

IPC: H01L23/498 ,  H01L25/065

Abstract: A microelectronic interposer for a microelectronic package may be fabricated, wherein a first microelectronic device within the microelectronic package is in electronic communication with at least one second microelectronic device through the microelectronic interposer which positions the at least one second microelectronic device outside a periphery of the first microelectronic device. The microelectronic interposer may further include at least one recess for achieving a desired height and/or enabling various configurations for the microelectronic package.

公开(公告)号：US20180076171A1

公开(公告)日：2018-03-15

申请号：US15262935

申请日：2016-09-12

Applicant: INTEL CORPORATION

Inventor： Navneet K. Singh ,  Ranjul Balakrishnan

IPC: H01L25/065 ,  H01L23/498

CPC classification number: H01L25/0652 ,  H01L23/49811 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572

Abstract: A microelectronic interposer for a microelectronic package may be fabricated, wherein a first microelectronic device within the microelectronic package is in electronic communication with at least one second microelectronic device through the microelectronic interposer which positions the at least one second microelectronic device outside a periphery of the first microelectronic device. The microelectronic interposer may further include at least one recess for achieving a desired height and/or enabling various configurations for the microelectronic package.

公开(公告)号：US11600544B2

公开(公告)日：2023-03-07

申请号：US16286736

申请日：2019-02-27

Applicant: INTEL CORPORATION

Inventor： Yogasundaram Chandiran ,  Geejagaaru Krishnamurthy Sandesh ,  Pradeep Ramesh ,  Ranjul Balakrishnan

IPC: H01L23/498 ,  H01L23/31 ,  H05K1/11 ,  H05K1/02 ,  H05K1/18

Abstract: A PCB having a first surface and a second surface includes a trench extending through the PCB, a plurality of conductive traces on one or more sidewalls of the trench. The plurality of conductive traces extends through the PCB and may be arranged in pairs across from one another along at least a portion of the length of the trench. A first set of conductive contacts are arranged in a first zig-zag pattern around a perimeter of the trench. A second set of conductive contacts are arranged in a second zig-zag pattern around the perimeter of the trench. In some cases, the first and second zig-zag patterns are arranged with respect to one another around the perimeter of the trench in an alternating fashion. A chip package is also disclosed having a pin arrangement that couples to the corresponding arrangement of conductive contacts on the PCB.

公开(公告)号：US10608311B2

公开(公告)日：2020-03-31

申请号：US15440983

申请日：2017-02-23

Applicant: Intel Corporation

Inventor： Arvind Sundaram ,  Ramaswamy Parthasarathy ,  Ranjul Balakrishnan ,  Vikas Mishra

IPC: H01P3/10 ,  H01R13/7193 ,  H01R43/24 ,  H01Q13/26 ,  H01R13/6477 ,  H01P5/08 ,  H01P1/36 ,  H01P11/00 ,  H01Q1/38 ,  H01Q1/42 ,  H01Q1/48 ,  H01Q13/02 ,  H01R4/18 ,  H01R13/24 ,  H05K1/18

Abstract: Embodiments of the present disclosure provide techniques and configurations for a cable assembly for single wire communications (SWC). In one instance, the cable assembly may comprise a wire having a wire end to couple with a signal launcher of an electronic device, and a first cover portion to house a first portion of the wire that extends from the wire end. The first cover portion may comprise a shape to conform to a shape of the signal launcher, and may be fabricated of a material with a dielectric constant above a threshold. The assembly may further comprise a second cover portion coupled with the first cover portion to house a second portion of the wire that extends from the first wire portion and protrudes from the first cover portion. The second cover portion may be fabricated of a ferrite material. Other embodiments may be described and/or claimed.

公开(公告)号：US20190206839A1

公开(公告)日：2019-07-04

申请号：US15859258

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Ranjul Balakrishnan ,  Navneet K. Singh ,  Bijendra Singh

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/367

CPC classification number: H01L25/0657 ,  H01L23/367 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include a heat spreader disposed between an electronic component and an electronic device. The heat spreader can be in thermal communication with the electronic component and operable to transfer heat from the electronic component to a lateral location beyond a first peripheral portion of the electronic component. Associated systems and methods are also disclosed.

公开(公告)号：US20190074281A1

公开(公告)日：2019-03-07

申请号：US16182972

申请日：2018-11-07

Applicant: Intel Corporation

Inventor： Navneet K. Singh ,  Shanto A. Thomas ,  Ranjul Balakrishnan

IPC: H01L27/11512 ,  H01L27/108 ,  H01L25/065 ,  H01L23/00

Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board, attaching a substrate on the die, wherein the substrate comprises a first region and a peripheral region, attaching a first memory device on the central region of the substrate, and attaching at least one additional memory device on the peripheral region of the substrate, wherein the at least one additional memory device is not disposed over the die.

公开(公告)号：US10177161B2

公开(公告)日：2019-01-08

申请号：US15392006

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Navneet K. Singh ,  Shanto A. Thomas ,  Ranjul Balakrishnan

IPC: H01L21/332 ,  H01L29/66 ,  H01L27/11512 ,  H01L27/108

Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board, attaching a substrate on the die, wherein the substrate comprises a first region and a peripheral region, attaching a first memory device on the central region of the substrate, and attaching at least one additional memory device on the peripheral region of the substrate, wherein the at least one additional memory device is not disposed over the die.

公开(公告)号：US20180182734A1

公开(公告)日：2018-06-28

申请号：US15392006

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Navneet K. Singh ,  Shanto A. Thomas ,  Ranjul Balakrishnan

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00

CPC classification number: H01L27/11512 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L27/10897 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181

Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board, attaching a substrate on the die, wherein the substrate comprises a first region and a peripheral region, attaching a first memory device on the central region of the substrate, and attaching at least one additional memory device on the peripheral region of the substrate, wherein the at least one additional memory device is not disposed over the die.