公开(公告)号：US20190237564A1

公开(公告)日：2019-08-01

申请号：US16344003

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： Chia-Hong JAN ,  Walid M. HAFEZ ,  Neville L. DIAS ,  Rahul RAMASWAMY ,  Hsu-Yu CHANG ,  Roman W. OLAC-VAW ,  Chen-Guan LEE

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66 ,  H01L29/66356 ,  H01L29/66818 ,  H01L29/7391 ,  H01L29/785 ,  H01L29/7851

Abstract: A transistor including a source and a drain each formed in a substrate; a channel disposed in the substrate between the source and drain, wherein the channel includes opposing sidewalls with a distance between the opposing sidewalls defining a width dimension of the channel and wherein the opposing sidewalls extend a distance below a surface of the substrate; and a gate electrode on the channel. A method of forming a transistor including forming a source and a drain in an area of a substrate; forming a source contact on the source and a drain contact on the drain; after forming the source contact and the drain contact, forming a channel in the substrate in an area between the source and drain, the channel including a body having opposing sidewalls separated by a length dimension; and forming a gate contact on the channel.

公开(公告)号：US20240038592A1

公开(公告)日：2024-02-01

申请号：US18378983

申请日：2023-10-11

Applicant: Intel Corporation

Inventor： Roman W. OLAC-VAW ,  Walid M. HAFEZ ,  Chia-Hong JAN ,  Pei-Chi LIU

IPC: H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L21/28 ,  H01L23/528 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8238

CPC classification number: H01L21/82345 ,  H01L27/1211 ,  H01L21/845 ,  H01L29/7855 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5283 ,  H01L27/0886 ,  H01L29/4966 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/66545

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US20190287972A1

公开(公告)日：2019-09-19

申请号：US16318316

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Roman W. OLAC-VAW ,  Chia-Hong JAN

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L23/48 ,  H01L21/768 ,  H01L21/8238

Abstract: Dual fin endcaps for self-aligned gate edge architectures, and methods of fabricating dual fin endcaps for self-aligned gate edge architectures, are described. In an example, a semiconductor structure includes an I/O device having a first plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation layer. A logic device having a second plurality of semiconductor fins is disposed above the substrate and protrudes through the uppermost surface of the trench isolation layer. A gate edge isolation structure is disposed between the I/O device and the logic device. A semiconductor fin of the first plurality of semiconductor fins closest to the gate edge isolation structure is spaced farther from the gate edge isolation structure than a semiconductor fin of the second plurality of semiconductor fins closest to the gate edge isolation structure.

公开(公告)号：US20190206980A1

公开(公告)日：2019-07-04

申请号：US16328704

申请日：2016-10-21

Applicant: Intel Corporation

Inventor： Chia-Hong JAN ,  Walid M. HAFEZ ,  Neville L. DIAS ,  Rahul RAMASWAMY ,  Hsu-Yu CHANG ,  Roman W. OLAC-VAW ,  Chen-Guan LEE

IPC: H01L49/02 ,  H01L21/306 ,  H01L21/285 ,  C23C16/455

CPC classification number: H01L28/24 ,  C23C16/45525 ,  H01L21/28556 ,  H01L21/30608 ,  H01L27/0629

Abstract: Fin-based thin film resistors, and methods of fabricating fin-based thin film resistors, are described. In an example, an integrated circuit structure includes a fin protruding through a trench isolation region above a substrate. The fin includes a semiconductor material and has a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end. An isolation layer is conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A resistor layer is conformal with the isolation layer conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A first anode cathode electrode is electrically connected to the resistor layer. A second anode or cathode electrode is electrically connected to the resistor layer.

公开(公告)号：US20190157153A1

公开(公告)日：2019-05-23

申请号：US16253760

申请日：2019-01-22

Applicant: Intel Corporation

Inventor： Roman W. OLAC-VAW ,  Walid M. HAFEZ ,  Chia-Hong JAN ,  Pei-Chi LIU

IPC: H01L21/8234 ,  H01L21/84 ,  H01L21/28 ,  H01L27/088 ,  H01L29/49 ,  H01L27/12 ,  H01L23/528

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.