公开(公告)号：US10559562B2

公开(公告)日：2020-02-11

申请号：US16360690

申请日：2019-03-21

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jin-Ping Han ,  Yulong Li ,  Dennis M. Newns ,  Paul M. Solomon ,  Xiao Sun

IPC分类号： H01L27/06 ,  H01L27/1159 ,  H01L21/28 ,  H01L27/11507 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51

摘要： A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.

公开(公告)号：US20180323188A1

公开(公告)日：2018-11-08

申请号：US15585876

申请日：2017-05-03

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jin-Ping Han ,  Yulong Li ,  Dennis M. Newns ,  Paul M. Solomon ,  Xiao Sun

IPC分类号： H01L27/06 ,  H01L29/51 ,  H01L29/49 ,  H01L29/06

CPC分类号： H01L27/0629 ,  H01L21/28291 ,  H01L27/11507 ,  H01L27/1159

摘要： A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.

公开(公告)号：US09934838B1

公开(公告)日：2018-04-03

申请号：US15591834

申请日：2017-05-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jin-Ping Han ,  Xiao Sun ,  Teng Yang

IPC分类号： G11C11/22 ,  G11C13/00 ,  G06N3/04 ,  G06N3/08

CPC分类号： G11C11/2273 ,  G06N3/04 ,  G06N3/084 ,  G11C11/223 ,  G11C11/2259 ,  G11C11/2275 ,  G11C11/2277 ,  G11C11/54 ,  G11C11/56 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/53

摘要： A memory unit cell and memory array device are provided. The memory unit cell includes a pulse adjustment circuit for providing an adjusted pulse with symmetric weight updating for a given state update in response to an input pulse and state feedback. The memory unit further includes a synapse element having a memory element with hysteresis for storing one of multiple possible states responsive to the adjusted pulse and for providing the state feedback to the pulse adjustment circuit.