公开(公告)号：US10818333B2

公开(公告)日：2020-10-27

申请号：US16550809

申请日：2019-08-26

申请人： International Business Machines Corporation

发明人： Jin Ping Han ,  Xiao Sun ,  Teng Yang

IPC分类号： G11C11/22 ,  H03K19/1776 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56 ,  G11C11/54 ,  G11C16/10 ,  G06N3/08 ,  G06N3/04 ,  G06N3/063 ,  G11C13/00

摘要： Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

公开(公告)号：US09934838B1

公开(公告)日：2018-04-03

申请号：US15591834

申请日：2017-05-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jin-Ping Han ,  Xiao Sun ,  Teng Yang

IPC分类号： G11C11/22 ,  G11C13/00 ,  G06N3/04 ,  G06N3/08

CPC分类号： G11C11/2273 ,  G06N3/04 ,  G06N3/084 ,  G11C11/223 ,  G11C11/2259 ,  G11C11/2275 ,  G11C11/2277 ,  G11C11/54 ,  G11C11/56 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/53

摘要： A memory unit cell and memory array device are provided. The memory unit cell includes a pulse adjustment circuit for providing an adjusted pulse with symmetric weight updating for a given state update in response to an input pulse and state feedback. The memory unit further includes a synapse element having a memory element with hysteresis for storing one of multiple possible states responsive to the adjusted pulse and for providing the state feedback to the pulse adjustment circuit.

公开(公告)号：US10395713B2

公开(公告)日：2019-08-27

申请号：US15859583

申请日：2017-12-31

申请人： International Business Machines Corporation

发明人： Jin Ping Han ,  Xiao Sun ,  Teng Yang

IPC分类号： G06N3/06 ,  G11C11/22 ,  H03K19/177

摘要： Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

公开(公告)号：US10381061B2

公开(公告)日：2019-08-13

申请号：US15717023

申请日：2017-09-27

申请人： International Business Machines Corporation

发明人： Jin Ping Han ,  Xiao Sun ,  Teng Yang

IPC分类号： G06N3/06 ,  G11C11/22 ,  H03K19/177

摘要： Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

公开(公告)号：US20190096463A1

公开(公告)日：2019-03-28

申请号：US15859583

申请日：2017-12-31

申请人： International Business Machines Corporation

发明人： Jin Ping Han ,  Xiao Sun ,  Teng Yang

IPC分类号： G11C11/22 ,  H03K19/177

CPC分类号： G11C11/223 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2275 ,  G11C11/54 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5657 ,  G11C11/5671 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  H03K19/1776

摘要： Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

公开(公告)号：US20190378555A1

公开(公告)日：2019-12-12

申请号：US16550809

申请日：2019-08-26

申请人： International Business Machines Corporation

发明人： Jin Ping Han ,  Xiao Sun ,  Teng Yang

IPC分类号： G11C11/22 ,  H03K19/177

摘要： Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

公开(公告)号：US20190096462A1

公开(公告)日：2019-03-28

申请号：US15717023

申请日：2017-09-27

申请人： International Business Machines Corporation

发明人： Jin Ping Han ,  Xiao Sun ,  Teng Yang

IPC分类号： G11C11/22 ,  H03K19/177

CPC分类号： G11C11/223 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2275 ,  G11C11/54 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5657 ,  G11C11/5671 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  H03K19/1776

摘要： Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.