利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

68 条记录 (耗时 0.027 秒)

    Metal gated ultra short MOSFET devices
    12.
    发明授权
    Metal gated ultra short MOSFET devices 失效
    金属门极超短MOSFET器件

    公开(公告)号：US07678638B2

    公开(公告)日：2010-03-16

    申请号：US12198857

    申请日：2008-08-26

    申请人： Jack Oon Chu ,  Bruce B. Doris ,  Meikei Ieong ,  Jing Wang

    发明人： Jack Oon Chu ,  Bruce B. Doris ,  Meikei Ieong ,  Jing Wang

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7838 ,  H01L21/28017 ,  H01L29/105

    摘要： MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.

    摘要翻译： 适用于栅极长度小于约40nm的MOSFET器件及其制造方法。 MOSFET器件包括由单晶Si基材料形成的接地平面。 Si基体层外延地设置在接地平面上。 体层掺杂了与地平面相反的杂质。 栅极具有中间功能函数的金属，其直接接触栅极绝缘体层。 栅极被图案化成小于约40nm，并且可能小于20nm的长度。 MOSFET的源极和漏极掺杂有与体层相同类型的掺杂剂。 在本发明的CMOS实施例中，NMOS和PMOS器件的栅极中的金属可以是相同的金属。

    LAYER TRANSFER OF LOW DEFECT SiGe USING AN ETCH-BACK PROCESS
    13.
    发明申请
    LAYER TRANSFER OF LOW DEFECT SiGe USING AN ETCH-BACK PROCESS 失效

    公开(公告)号：US20090267052A1

    公开(公告)日：2009-10-29

    申请号：US12181613

    申请日：2008-07-29

    申请人： Jack Oon Chu ,  David R. DiMilia ,  Lijuan Huang

    发明人： Jack Oon Chu ,  David R. DiMilia ,  Lijuan Huang

    IPC分类号： H01L29/12

    CPC分类号： H01L21/76256 ,  H01L21/2007

    摘要： A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) or a SiGe on Si heterostructure is described incorporating growing epitaxial Si1-yGey layers on a semiconductor substrate, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and transferring the SiGe layer from one substrate to the other via highly selective etching using SiGe itself as the etch-stop. The transferred SiGe layer may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1-yGey, and strained Si1-yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1-yGeyC or a heavily doped layer to make electrical contacts for the SiGe/Si heterojunction diodes.

    Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof
    14.
    发明授权
    Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof 失效
    超可伸缩高速异质结垂直n沟道MISFET及其方法

    公开(公告)号：US07453113B2

    公开(公告)日：2008-11-18

    申请号：US11735711

    申请日：2007-04-16

    申请人： Qiqing Christine Ouyang ,  Jack Oon Chu

    发明人： Qiqing Christine Ouyang ,  Jack Oon Chu

    IPC分类号： H01L27/108

    CPC分类号： H01L29/7781 ,  H01L29/161 ,  H01L29/165 ,  H01L29/778 ,  H01L29/7782 ,  H01L29/7789 ,  H01L29/7828 ,  H01L29/78642 ,  H01L29/78687

    摘要： A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.

    摘要翻译： 描述了一种用于形成场效应晶体管，场效应晶体管和CMOS电路的应变垂直沟道的方法，其中在垂直单晶半导体结构的侧壁上结合有漏极，主体和源极区域，其中异质结 形成在晶体管的源极和主体之间，其中源极区域和沟道相对于主体区域独立地晶格应变，并且其中漏极区域包含碳掺杂区域以防止掺杂剂（硼）扩散到体内。 本发明通过异质结和晶格应变来减少来自源极区域的漏电流的问题，同时通过选择半导体材料独立地允许沟道区域中的晶格应变以增加迁移率。

    Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof
    16.
    发明授权
    Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof 有权
    超可伸缩高速异质结垂直n沟道MISFET及其方法

    公开(公告)号：US07205604B2

    公开(公告)日：2007-04-17

    申请号：US10463038

    申请日：2003-06-17

    申请人： Qiqing Christine Ouyang ,  Jack Oon Chu

    发明人： Qiqing Christine Ouyang ,  Jack Oon Chu

    IPC分类号： H01L29/94

    CPC分类号： H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/778 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/7789 ,  H01L29/7828

    摘要： A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a heterojunction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the heterojunction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.

    摘要翻译： 描述了形成场效应晶体管，场效应晶体管和CMOS电路的应变垂直沟道的方法，其中在垂直单晶半导体结构的侧壁上结合有漏极，主体和源极区域，其中形成异质结 在晶体管的源极和主体之间，其中源极区域和沟道相对于体区域独立地晶格应变，并且其中漏极区域包含碳掺杂区域以防止掺杂剂（硼）扩散到体内。 本发明通过异质结和晶格应变来减少来自源区的漏电流的问题，同时通过选择半导体材料独立地允许沟道区中的晶格应变以增加迁移率。

    Transferable device-containing layer for silicon-on-insulator applications
    17.
    发明授权
    Transferable device-containing layer for silicon-on-insulator applications 失效

    公开(公告)号：US07038277B2

    公开(公告)日：2006-05-02

    申请号：US10826712

    申请日：2004-04-16

    申请人： Jack Oon Chu ,  Alfred Grill ,  Dean A. Herman, Jr. ,  Katherine L. Saenger

    发明人： Jack Oon Chu ,  Alfred Grill ,  Dean A. Herman, Jr. ,  Katherine L. Saenger

    IPC分类号： H01L27/01

    CPC分类号： H01L27/1203 ,  H01L21/76259

    摘要： A method for forming an integrated circuit on an insulating substrate is described comprising the steps of forming a semiconductor layer on a seed wafer substrate containing an at least partially crystalline porous release layer, processing the semiconductor layer to form a “transferable” device layer containing at least one semiconductor device, and bonding said transferable device layer to a final, insulating substrate before or after separating said device layer from the seed wafer substrate. A second method, for separating a semiconductor layer from a seed wafer substrate, is described wherein an at least partially crystalline porous layer initially connecting the semiconductor layer and seed wafer substrate is split or broken apart by the steps of (i) introducing a fluid including water into the pores of said porous layer, and (ii) expanding said fluid by solidifying or freezing to break apart the porous layer. The at least partially crystalline porous layer may incorporate at least one porous silicon germanium alloy layer alone or in combination with at least one porous Si layer. Also described is an integrated circuit comprising the transfered device layer described above.

    In-situ monitoring and control of germanium profile in silicon-germanium alloy films and temperature monitoring during deposition of silicon films
    19.
    发明授权
    In-situ monitoring and control of germanium profile in silicon-germanium alloy films and temperature monitoring during deposition of silicon films 失效
    原位监测和控制硅锗合金薄膜中的锗分布以及淀积硅膜期间的温度监测

    公开(公告)号：US06881259B1

    公开(公告)日：2005-04-19

    申请号：US09633857

    申请日：2000-08-07

    申请人： David C. Ahlgren ,  Jack Oon Chu ,  Basanth Jagannathan ,  Ryan W. Wuthrich

    发明人： David C. Ahlgren ,  Jack Oon Chu ,  Basanth Jagannathan ,  Ryan W. Wuthrich

    IPC分类号： C30B25/16 ,  C30B29/52

    CPC分类号： C30B29/52 ,  C30B25/165

    摘要： Analysis of residual gases from a process for depositing a film containing silicon on a crystalline silicon surface to determine partial pressure of hydrogen evolved during deposition develops a signature which indicates temperature and/or concentration of germanium at the deposition surface. Calibration and collection of hydrogen partial pressure data at a rate which is high relative to film deposition rate allows real-time, in-situ, non-destructive determination of material concentration profile over the thickness of the film and/or monitoring the temperature of a silicon film deposition process with increased accuracy and resolution to provide films of a desired thickness with high accuracy.

    摘要翻译： 分析来自用于在晶体硅表面上沉积含硅的膜的工艺的残余气体，以确定在沉积期间释放出来的氢的分压，形成指示沉积表面的锗的温度和/或浓度的标记。 以相对于膜沉积速率高的速率校准和收集氢分压数据允许在膜的厚度上的材料浓度分布的实时，原位，非破坏性测定和/或监测膜的温度 硅膜沉积工艺具有更高的精度和分辨率，以高精度提供所需厚度的膜。