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    Formation of spacers for FinFETs (Field Effect Transistors)
    6.
    发明授权
    Formation of spacers for FinFETs (Field Effect Transistors) 有权
    FinFET间隔物的形成（场效应晶体管）

    公开(公告)号：US07399664B1

    公开(公告)日：2008-07-15

    申请号：US11679862

    申请日：2007-02-28

    申请人： Brent Alan Anderson ,  Edward Joseph Nowak ,  Kathryn Turner Schonenberg

    发明人： Brent Alan Anderson ,  Edward Joseph Nowak ,  Kathryn Turner Schonenberg

    IPC分类号： H01L21/84 ,  H01L21/00 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/4763 ,  H01L21/3205

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： A structure and a method for forming the same. The structure includes (a) a substrate, (b) a semiconductor fin region on top of the substrate, (c) a gate dielectric region on side walls of the semiconductor fin region, and (d) a gate electrode region on top and on side walls of the semiconductor fin region. The gate dielectric region (i) is sandwiched between and (ii) electrically insulates the gate electrode region and the semiconductor fin region. The structure further includes a first spacer region on a first side wall of the gate electrode region. A first side wall of the semiconductor fin region is exposed to a surrounding ambient. A top surface of the first spacer region is coplanar with a top surface of the gate electrode region.

    摘要翻译： 一种结构及其形成方法。 该结构包括（a）衬底，（b）在衬底的顶部上的半导体鳍片区域，（c）半导体鳍片区域的侧壁上的栅极电介质区域，以及（d）顶部和上部的栅电极区域 半导体鳍片区域的侧壁。 栅极电介质区域（i）夹在其间并且（ii）使栅电极区域和半导体鳍片区域电绝缘。 该结构还包括在栅电极区域的第一侧壁上的第一间隔区域。 半导体鳍片区域的第一侧壁暴露于周围环境。 第一间隔区域的顶表面与栅电极区域的顶表面共面。

    BIPOLAR TRANSISTOR WITH LOW RESISTANCE BASE CONTACT AND METHOD OF MAKING THE SAME
    7.
    发明申请
    BIPOLAR TRANSISTOR WITH LOW RESISTANCE BASE CONTACT AND METHOD OF MAKING THE SAME 审中-公开
    具有低电阻基底接触的双极晶体管及其制造方法

    公开(公告)号：US20090065804A1

    公开(公告)日：2009-03-12

    申请号：US11852507

    申请日：2007-09-10

    申请人： Francois Pagette ,  Kathryn Turner Schonenberg

    发明人： Francois Pagette ,  Kathryn Turner Schonenberg

    IPC分类号： H01L29/737 ,  H01L21/331

    CPC分类号： H01L29/66242 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/7371

    摘要： Embodiments of the present invention provide a bipolar transistor with low resistance base contact and method of manufacturing the same. The bipolar transistor includes an emitter, a collector, and an intrinsic base between the emitter and the collector. The intrinsic base extends laterally to an extrinsic base. The extrinsic base further includes a first semiconductor material with a first bandgap and a second semiconductor material with a second bandgap that is smaller than the first bandgap.

    摘要翻译： 本发明的实施例提供一种具有低电阻基极触点的双极晶体管及其制造方法。 双极晶体管包括在发射极和集电极之间的发射极，集电极和本征基极。 本征基础横向扩展到外在基础。 外部基极还包括具有第一带隙的第一半导体材料和具有小于第一带隙的第二带隙的第二半导体材料。

    Bipolar transistor with low resistance base contact
    9.
    发明授权
    Bipolar transistor with low resistance base contact 有权
    具有低电阻基极触点的双极晶体管

    公开(公告)号：US08357953B2

    公开(公告)日：2013-01-22

    申请号：US12535310

    申请日：2009-08-04

    申请人： Francois Pagette ,  Kathryn Turner Schonenberg

    发明人： Francois Pagette ,  Kathryn Turner Schonenberg

    IPC分类号： H01L29/739

    CPC分类号： H01L29/66242 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/7371

    摘要： Embodiments of the present invention provide a bipolar transistor with low resistance base contact and method of manufacturing the same. The bipolar transistor includes an emitter, a collector, and an intrinsic base between the emitter and the collector. The intrinsic base extends laterally to an extrinsic base. The extrinsic base further includes a first semiconductor material with a first bandgap and a second semiconductor material with a second bandgap that is smaller than the first bandgap.

    摘要翻译： 本发明的实施例提供一种具有低电阻基极触点的双极晶体管及其制造方法。 双极晶体管包括在发射极和集电极之间的发射极，集电极和本征基极。 本征基础横向扩展到外在基础。 外部基极还包括具有第一带隙的第一半导体材料和具有小于第一带隙的第二带隙的第二半导体材料。

    Bipolar transistor structure with a shallow isolation extension region providing reduced parasitic capacitance
    10.
    发明授权
    Bipolar transistor structure with a shallow isolation extension region providing reduced parasitic capacitance 失效
    具有浅隔离延伸区域的双极晶体管结构，提供降低的寄生电容

    公开(公告)号：US06864560B2

    公开(公告)日：2005-03-08

    申请号：US10249299

    申请日：2003-03-28

    申请人： Marwan H. Khater ,  Jae-Sung Rieh ,  Andreas Daniel Stricker ,  Gregory Gower Freeman ,  Kathryn Turner Schonenberg

    发明人： Marwan H. Khater ,  Jae-Sung Rieh ,  Andreas Daniel Stricker ,  Gregory Gower Freeman ,  Kathryn Turner Schonenberg

    IPC分类号： H01L29/70 ,  H01L21/331 ,  H01L29/732 ,  H01L29/737 ,  H01L27/082 ,  H01L27/102 ,  H01L31/11

    CPC分类号： H01L29/66287 ,  H01L29/0649 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

    摘要： A bipolar vertical transistor is formed in a silicon semiconductor substrate which has an upper surface with STI regions formed therein composed of a dielectric material formed in the substrate having inner ends and top surfaces. A doped collector region is formed in the substrate between a pair of the STI regions. A counterdoped intrinsic base region is formed on the upper surface of the substrate between the pair of the STI regions with a margin between the intrinsic base region and the pair of STI regions, the intrinsic base region having edges. A doped emitter region is formed above the intrinsic base region spaced away from the edges. A shallow isolation extension region composed of a dielectric material is next to the edges of the intrinsic base region formed in the margin between the STI regions and the intrinsic base region. An extrinsic base region covers the shallow isolation extension region and extends partially over the intrinsic base region in mechanical and electrical contact therewith, whereby the shallow isolation extension region reduces the base-to-collector parasitic capacitance of the bipolar transistor.

    摘要翻译： 双极性垂直晶体管形成在硅半导体衬底中，该硅半导体衬底具有形成有STI区域的上表面，该区域由形成在具有内端和顶表面的衬底中的电介质材料构成。 掺杂的集电极区域形成在一对STI区域之间的衬底中。 在本体基极区域和一对STI区域之间的边缘部分之间形成反向掺杂的本征基极区域，该反向掺杂的本征基极区域位于一对STI区域之间的衬底的上表面上，本征基极区域具有边缘。 掺杂的发射极区域形成在与边缘间隔开的本征基极区域上方。 由介电材料构成的浅隔离延伸区域紧邻在STI区域和本征基极区域之间的边缘中形成的本征基极区域的边缘。 外部基极区域覆盖浅隔离延伸区域并且在与本体基极区域机械和电接触的同时部分延伸，由此浅隔离延伸区域减小双极晶体管的基极到集电极寄生电容。