公开(公告)号：US06881259B1

公开(公告)日：2005-04-19

申请号：US09633857

申请日：2000-08-07

申请人： David C. Ahlgren ,  Jack Oon Chu ,  Basanth Jagannathan ,  Ryan W. Wuthrich

发明人： David C. Ahlgren ,  Jack Oon Chu ,  Basanth Jagannathan ,  Ryan W. Wuthrich

IPC分类号： C30B25/16 ,  C30B29/52

CPC分类号： C30B29/52 ,  C30B25/165

摘要： Analysis of residual gases from a process for depositing a film containing silicon on a crystalline silicon surface to determine partial pressure of hydrogen evolved during deposition develops a signature which indicates temperature and/or concentration of germanium at the deposition surface. Calibration and collection of hydrogen partial pressure data at a rate which is high relative to film deposition rate allows real-time, in-situ, non-destructive determination of material concentration profile over the thickness of the film and/or monitoring the temperature of a silicon film deposition process with increased accuracy and resolution to provide films of a desired thickness with high accuracy.

摘要翻译： 分析来自用于在晶体硅表面上沉积含硅的膜的工艺的残余气体，以确定在沉积期间释放出来的氢的分压，形成指示沉积表面的锗的温度和/或浓度的标记。 以相对于膜沉积速率高的速率校准和收集氢分压数据允许在膜的厚度上的材料浓度分布的实时，原位，非破坏性测定和/或监测膜的温度 硅膜沉积工艺具有更高的精度和分辨率，以高精度提供所需厚度的膜。

公开(公告)号：US06858532B2

公开(公告)日：2005-02-22

申请号：US10316211

申请日：2002-12-10

申请人： Wesley C. Natzle ,  David C. Ahlgren ,  Steven G. Barbee ,  Marc W. Cantell ,  Basanth Jagannathan ,  Louis D. Lanzerotti ,  Seshadri Subbanna ,  Ryan W. Wuthrich

发明人： Wesley C. Natzle ,  David C. Ahlgren ,  Steven G. Barbee ,  Marc W. Cantell ,  Basanth Jagannathan ,  Louis D. Lanzerotti ,  Seshadri Subbanna ,  Ryan W. Wuthrich

IPC分类号： H01L21/302 ,  H01L21/311 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/732 ,  H01L21/4763

CPC分类号： H01L29/66242 ,  H01L21/31116 ,  H01L21/8249

摘要： An oxide etch process is described which may be used for emitter and base preparation in bipolar SiGe devices. The low temperature process employed produces electrical insulation between the emitter and base by a COR etch which preserves insulating TEOS glass. The insulating TEOS glass provides reduced capacitance and helps to achieve high speed. An apparatus is also described for practicing the disclosed process.

摘要翻译： 描述了氧化物蚀刻工艺，其可用于双极SiGe器件中的发射极和基极准备。 所采用的低温工艺通过保留绝缘TEOS玻璃的COR蚀刻产生发射极和基极之间的电绝缘。 绝缘TEOS玻璃提供降低的电容并有助于实现高速度。 还描述了用于实施所公开的方法的装置。

公开(公告)号：US06780735B2

公开(公告)日：2004-08-24

申请号：US09843783

申请日：2001-04-30

申请人： Basanth Jagannathan ,  Jack O. Chu ,  Ryan W. Wuthrich ,  Byeongju Park

发明人： Basanth Jagannathan ,  Jack O. Chu ,  Ryan W. Wuthrich ,  Byeongju Park

IPC分类号： H01L2104

CPC分类号： C30B29/06 ,  C30B25/02 ,  C30B29/08 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02579 ,  H01L21/0262

摘要： We provide a method of doping an Si or SiGe film with carbon or boron. By reducing the silicon precursor pressure, heavily-doped films may be obtained. A single dopant source may be used. The doped Si and SiGe films are of suitable quality for use in a transistor such as an HBT.

摘要翻译： 我们提供了用碳或硼掺杂Si或SiGe膜的方法。 通过降低硅前体压力，可以获得重掺杂的膜。 可以使用单个掺杂剂源。 掺杂的Si和SiGe膜具有适用于诸如HBT之类的晶体管的质量。

公开(公告)号：US06744079B2

公开(公告)日：2004-06-01

申请号：US09683983

申请日：2002-03-08

申请人： Basanth Jagannathan ,  Alvin J. Joseph ,  Xuefeng Liu ,  Kathryn T. Schonenberg ,  Ryan W. Wuthrich

发明人： Basanth Jagannathan ,  Alvin J. Joseph ,  Xuefeng Liu ,  Kathryn T. Schonenberg ,  Ryan W. Wuthrich

IPC分类号： H01L31072

CPC分类号： H01L29/66242 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/7378

摘要： A high performance SiGe HBT that has a SiGe layer with a peak Ge concentration of at least approximately 20% and a boron-doped base region formed therein having a thickness. The base region includes diffusion-limiting impurities substantially throughout its thickness, at a peak concentration below that of boron in the base region. Both the base region and the diffusion-limiting impurities are positioned relative to a peak concentration of Ge in the SiGe layer so as to optimize both performance and yield.

摘要翻译： 具有峰值Ge浓度至少为20％的SiGe层和其中形成有硼掺杂基底区域的高性能SiGe HBT具有厚度。 碱性区域在其整个厚度上基本上包括扩散限制性杂质，峰值浓度低于碱性区域中硼的峰值浓度。 碱性区域和扩散限制杂质都相对于SiGe层中的Ge的峰值浓度定位，以便优化性能和产率。

公开(公告)号：US06774000B2

公开(公告)日：2004-08-10

申请号：US10300239

申请日：2002-11-20

申请人： Wesley C. Natzle ,  Marc W. Cantell ,  Louis D. Lanzerotti ,  Effendi Leobandung ,  Brian L. Tessier ,  Ryan W. Wuthrich

发明人： Wesley C. Natzle ,  Marc W. Cantell ,  Louis D. Lanzerotti ,  Effendi Leobandung ,  Brian L. Tessier ,  Ryan W. Wuthrich

IPC分类号： H01L21336

CPC分类号： H01L21/31116 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/28525 ,  H01L21/28562 ,  H01L29/66628

摘要： A process for manufacturing an FET device. A semiconductor substrate is covered with a gate dielectric layer and with a conductive gate electrode formed over the gate dielectric. Blanket layers of silicon oxide may be added. An optional collar of silicon nitride may be formed over the silicon oxide layer around the gate electrode. Two precleaning steps are performed. Chemical oxide removal gases are then deposited, covering the device with an adsorbed reactant film. The gate dielectric (aside from the gate electrode) is removed, as the adsorbed reactant film reacts with the gate dielectric layer to form a rounded corner of silicon oxide at the base of the gate electrode. One or two in-situ doped silicon layers are deposited over the source/drain regions to form single or laminated epitaxial raised source/drain regions over the substrate protruding beyond the surface of the gate dielectric.

公开(公告)号：US06900519B2

公开(公告)日：2005-05-31

申请号：US10865138

申请日：2004-06-10

申请人： Marc W. Cantell ,  James S. Dunn ,  David L. Harame ,  Robb A. Johnson ,  Louis D. Lanzerotti ,  Stephen A. St. Onge ,  Brian L. Tessier ,  Ryan W. Wuthrich

发明人： Marc W. Cantell ,  James S. Dunn ,  David L. Harame ,  Robb A. Johnson ,  Louis D. Lanzerotti ,  Stephen A. St. Onge ,  Brian L. Tessier ,  Ryan W. Wuthrich

IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L29/10 ,  H01L27/082

CPC分类号： H01L29/66287 ,  H01L21/8249 ,  H01L29/1004

摘要： The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device. Additionally, the extrinsic base can be formed with a self-aligned manufacturing process that reduces fabrication complexity.

公开(公告)号：US07118995B2

公开(公告)日：2006-10-10

申请号：US10709644

申请日：2004-05-19

申请人： Mark D. Dupuis ,  Wade J. Hodge ,  Daniel T. Kelly ,  Ryan W. Wuthrich

发明人： Mark D. Dupuis ,  Wade J. Hodge ,  Daniel T. Kelly ,  Ryan W. Wuthrich

IPC分类号： H01L21/20

CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639

摘要： A method for determining a SiGe deposition condition so as to improve yield of a semiconductor structure. Fabrication of the semiconductor structure starts with a single-crystal silicon (Si) layer. Then, first and second shallow trench isolation (STI) regions are formed in the single-crystal Si layer. The STI regions sandwich and define a first single-crystal Si region. Next, silicon-germanium (SiGe) mixture is deposited on top of the structure in a SiGe deposition condition so as to grow (i) a second single-crystal silicon region grows up from the top surface of the first single-crystal silicon region and (ii) first and second polysilicon regions from the top surfaces of the first and second STI regions, respectively. By increasing SiGe deposition temperature and/or lowering precursor flow rate until the resulting yield is within a pre-specified range, a satisfactory SiGe deposition condition can be determined for mass production of the structure.

摘要翻译： 一种用于确定SiGe沉积条件以提高半导体结构的产量的方法。 半导体结构的制造以单晶硅（Si）层开始。 然后，在单晶Si层中形成第一和第二浅沟槽隔离（STI）区域。 STI区域夹持并限定第一单晶Si区域。 接下来，硅锗（SiGe）混合物以SiGe沉积条件沉积在结构的顶部，以便生长（i）第二单晶硅区域从第一单晶硅区域的顶表面生长， （ii）分别来自第一和第二STI区域的顶表面的第一和第二多晶硅区域。 通过提高SiGe沉积温度和/或降低前驱体流速直到得到的产率达到预定范围内，可以确定满足SiGe沉积条件以进行大规模生产。

公开(公告)号：US06869854B2

公开(公告)日：2005-03-22

申请号：US10064476

申请日：2002-07-18

申请人： Marc W. Cantell ,  James S. Dunn ,  David L. Harame ,  Robb A. Johnson ,  Louis D. Lanzerotti ,  Stephen A. St. Onge ,  Brian L. Tessier ,  Ryan W. Wuthrich

发明人： Marc W. Cantell ,  James S. Dunn ,  David L. Harame ,  Robb A. Johnson ,  Louis D. Lanzerotti ,  Stephen A. St. Onge ,  Brian L. Tessier ,  Ryan W. Wuthrich

IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L29/10 ,  H01L23/62

CPC分类号： H01L29/66287 ,  H01L21/8249 ,  H01L29/1004

摘要： The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device. Additionally, the extrinsic base can be formed with a self-aligned manufacturing process that reduces fabrication complexity.

摘要翻译： 本发明提供了在集成双极性电路器件中提供增加的晶体管性能的独特的器件结构和方法。 本发明的优选实施例通过提供降低的基极电阻来提供改进的高速性能。 优选的设计通过将掺杂剂从掺杂剂源层扩散到外部碱性区域中形成外部碱基。 掺杂剂的这种扩散形成至少一部分外在碱。 特别地，通过扩散形成与本征基区相邻的部分。 该解决方案避免了植入外在基础的传统解决方案所引起的问题。 具体地说，通过扩散形成外部基体的至少一部分，能够使基部区域的损伤问题最小化。 这种降低的损伤增强了掺杂剂扩散到本征基质中。 另外，形成的外部基极可以具有改善的电阻，导致双极器件的最大频率改善。 另外，外部基座可以通过降低制造复杂性的自对准制造工艺来形成。

公开(公告)号：US06858903B2

公开(公告)日：2005-02-22

申请号：US10881449

申请日：2004-06-30

申请人： Wesley C. Natzle ,  Marc W. Cantell ,  Louis D. Lanzerotti ,  Effendi Leobandung ,  Brian L. Tessier ,  Ryan W. Wuthrich

发明人： Wesley C. Natzle ,  Marc W. Cantell ,  Louis D. Lanzerotti ,  Effendi Leobandung ,  Brian L. Tessier ,  Ryan W. Wuthrich

IPC分类号： H01L21/20 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L27/76

CPC分类号： H01L21/31116 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/28525 ,  H01L21/28562 ,  H01L29/66628

摘要： A process for manufacturing an FET device. A semiconductor substrate is covered with a gate dielectric layer and with a conductive gate electrode formed over the gate dielectric. Blanket layers of silicon oxide may be added. An optional collar of silicon nitride may be formed over the silicon oxide layer around the gate electrode. Two precleaning steps are performed. Chemical oxide removal gases are then deposited, covering the device with an adsorbed reactant film. The gate dielectric (aside from the gate electrode) is removed, as the adsorbed reactant film reacts with the gate dielectric layer to form a rounded corner of silicon oxide at the base of the gate electrode. One or two in-situ doped silicon layers are deposited over the source/drain regions to form single or laminated epitaxial raised source/drain regions over the substrate protruding beyond the surface of the gate dielectric.

摘要翻译： 一种用于制造FET器件的工艺。 半导体衬底被栅极电介质层覆盖，并且在栅极电介质上形成导电栅电极。 可以加入氧化硅的毯层。 可以在栅电极周围的氧化硅层上形成可选的氮化硅环。 执行两个预清洗步骤。 然后沉积化学氧化物去除气体，用吸附的反应物膜覆盖该装置。 由于吸附的反应物膜与栅极电介质层反应，在栅电极的底部形成氧化硅的圆角，所以除去栅极电介质（除了栅电极之外）。 一个或两个原位掺杂的硅层沉积在源极/漏极区上，以在衬底上方突出超过栅极电介质的表面形成单个或层叠的外延凸起的源/漏区。

公开(公告)号：US5948193A

公开(公告)日：1999-09-07

申请号：US886032

申请日：1997-06-30

申请人： Michael A. Cohn ,  Jon A. Casey ,  Christopher N. Collins ,  Robert A. Rita ,  Robert J. Sullivan ,  Adrienne M. Tirch ,  Leslie J. Wiands ,  Ryan W. Wuthrich

发明人： Michael A. Cohn ,  Jon A. Casey ,  Christopher N. Collins ,  Robert A. Rita ,  Robert J. Sullivan ,  Adrienne M. Tirch ,  Leslie J. Wiands ,  Ryan W. Wuthrich

IPC分类号： C04B35/622 ,  B28B1/30 ,  B32B18/00 ,  H01G4/30 ,  H01L21/48 ,  H05K1/03 ,  H05K3/46 ,  B32B31/26

CPC分类号： B32B18/00 ,  H01L21/4857 ,  C04B2235/6567 ,  C04B2235/658 ,  C04B2237/12 ,  C04B2237/343 ,  C04B2237/704 ,  H05K1/0306 ,  H05K3/4629

摘要： Greensheets having enhanced flexibility and strength are prepared from a greensheet casting composition comprising alumina or other ceramic having a mean particle size of less than about 1 micron and being substantially unimodal, a binder resin, a solvent system and a plasticizer. The greensheets may be formed having a thickness of about 50 microns using conventional greensheet fabricating devices. The greensheets are particularly suitable as dielectric layers for internal layer capacitors in a multilayer ceramic substrate. A preferred co-sintering heating profile to avoid blistering of the MLC package is also provided to form the capacitor containing MLC.

摘要翻译： 具有增强的柔韧性和强度的格式纸由包含氧化铝或平均粒径小于约1微米并且基本上单峰的其它陶瓷，粘合剂树脂，溶剂体系和增塑剂的毛坯铸塑组合物制备。 可以使用常规的毛坯制造装置形成厚度为约50微米的毛坯。 毛坯特别适合作为多层陶瓷基板中的内层电容器的介电层。 还提供了优选的共烧结加热曲线，以避免MLC封装的起泡，以形成包含MLC的电容器。