-
11.发明授权Method and system for executing a context-altering instruction without performing a context-synchronization operation within high-performance processors 失效用于执行上下文改变指令而不在高性能处理器内执行上下文同步操作的方法和系统
公开(公告)号：US5898864A
公开(公告)日：1999-04-27
申请号：US918059
申请日：1997-08-25
CPC分类号： G06F9/3863 , G06F9/3842
摘要： A method and system for executing a context-altering instruction within a processor are disclosed. The processor has a superscalar architecture that includes multiple pipelines, buffers, registers, and execution units. The processor also includes a machine state register for identifying a context of the processor, and a shadow machine state register in conjunction with the machine state register. During operation, a first state of the machine state register is copied to the shadow machine state register. Instructions are executed in accordance with a context identified by the first state of the machine state register. The first state of the shadow machine state register is subsequently altered to a second state in response to decoding a context-altering instruction. The context-altering instruction and subsequent instructions are then executed in accordance with the second state of the shadow machine state register. Finally, the first state of the machine state register is altered to the second state in response to a completion of the context-altering instruction. As a result context synchronization operations are avoided.
摘要翻译： 公开了一种用于在处理器内执行上下文更改指令的方法和系统。 处理器具有超标量架构，其包括多个管道，缓冲器，寄存器和执行单元。 处理器还包括用于识别处理器的上下文的机器状态寄存器和与机器状态寄存器一起的影子机状态寄存器。 在运行期间，机器状态寄存器的第一个状态被复制到影子机状态寄存器。 根据由机器状态寄存器的第一状态识别的上下文来执行指令。 响应于解码上下文改变指令，影子机状态寄存器的第一状态随后被改变到第二状态。 然后根据影子机状态寄存器的第二状态执行上下文改变指令和随后的指令。 最后，响应于上下文改变指令的完成，机器状态寄存器的第一状态被改变到第二状态。 因此，避免了上下文同步操作。
-
12.发明授权Method and system for recording noneffective instructions within a data processing system 失效在数据处理系统中记录无效指令的方法和系统
公开(公告)号：US5717587A
公开(公告)日：1998-02-10
申请号：US649753
申请日：1996-05-15
申请人： Bryan Black , Marvin A. Denman , Lee E. Eisen , Robert T. Golla , Albert J. Loper, Jr. , Soummya Mallick , Russell Adley Reininger
发明人： Bryan Black , Marvin A. Denman , Lee E. Eisen , Robert T. Golla , Albert J. Loper, Jr. , Soummya Mallick , Russell Adley Reininger
CPC分类号： G06F9/3017 , G06F9/30145
摘要： A method and system are disclosed for processing instructions within a data processing system including a processor having a plurality of execution units. According to the method of the present invention, a number of instructions stored within a memory within the data processing system are retrieved from memory. A selected instruction among the number of instructions is decoded to determine if the selected instruction would be noneffective if executed by the processor. In a preferred embodiment of the present invention, noneffective instructions include instructions with invalid opcodes and instructions that would not change the value of any data register within the processor. In response to determining that the selected instruction would be noneffective if executed by the processor, the selected instruction is recoded into a specified instruction format prior to dispatching the selected instruction to one of the number of execution units. Detecting noneffective instructions prior to dispatch reduces the decode logic required within the dispatcher and enhances processor performance.
摘要翻译： 公开了一种用于处理包括具有多个执行单元的处理器的数据处理系统内的指令的方法和系统。 根据本发明的方法，从存储器中检索存储在数据处理系统内的存储器内的多个指令。 解码指令数目中的选择指令，以确定所选择的指令是否由处理器执行时是无效的。 在本发明的优选实施例中，无效指令包括具有无效操作码的指令和不会改变处理器内的任何数据寄存器的值的指令。 响应于确定所选择的指令如果由处理器执行将是无效的，则在将所选择的指令分派到多个执行单元之一之前，所选择的指令被重新编码为指定的指令格式。 在调度之前检测无效指令可减少调度程序中所需的解码逻辑，并提高处理器的性能。
-
13.发明授权Method for executing speculative load instructions in high-performance processors 失效在高性能处理器中执行推测加载指令的方法
公开(公告)号：US5611063A
公开(公告)日：1997-03-11
申请号：US597647
申请日：1996-02-06
CPC分类号： G06F9/30043 , G06F9/383 , G06F9/3842
摘要： A method for selectively executing speculative load instructions in a high-performance processor is disclosed. In accordance with the present disclosure, when a speculative load instruction for which the data is not stored in a data cache is encountered, a bit within an enable speculative load table which is associated with that particular speculative load instruction is read in order to determine a state of the bit. If the associated bit is in a first state, data for the speculative load instruction is requested from a system bus and further execution of the speculative load instruction is then suspended to wait for control signals from a branch processing unit. If the associated bit is in a second state, the execution of the speculative load instruction is immediately suspended to wait for control signals from the branch processing unit. If the speculative load instruction is executed in response to the control signals, then the associated bit in the enable speculative load table will be set to the first state. However, if the speculative load instruction is not executed in response to the control signals, then the associated bit in the enable speculative load table is set to the second state. In this manner, the displacement of useful data in the data cache due to wrongful execution of the speculative load instruction is avoided.
摘要翻译： 公开了一种用于选择性地执行高性能处理器中的推测性加载指令的方法。 根据本公开，当遇到数据未被存储在数据高速缓冲存储器中的推测性加载指令时，读取与该特定推测加载指令相关联的使能投机载入表中的位，以便确定 状态的位。 如果关联位处于第一状态，则从系统总线请求用于推测加载指令的数据，然后暂停推测加载指令的进一步执行，以等待来自分支处理单元的控制信号。 如果相关联的位处于第二状态，则推测加载指令的执行被立即停止，以等待来自分支处理单元的控制信号。 如果响应于控制信号执行推测加载指令，则使能推测加载表中的关联位将被设置为第一状态。 然而，如果不响应于控制信号执行推测加载指令，则使能推测负载表中的关联位被设置为第二状态。 以这种方式，避免了由于推测加载指令的错误执行而在数据高速缓存中的有用数据的位移。
-
14.发明授权
公开(公告)号：US5867684A
公开(公告)日：1999-02-02
申请号：US873013
申请日：1997-06-11
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3834 , G06F9/3838
摘要： A method and device of executing a load multiple instruction in a superscaler microprocessor is provided. The method comprises the steps of dispatching a load multiple instruction to a load/store unit, wherein the load/store unit begins execution of a dispatched load multiple instruction, and wherein the load multiple instruction loads data from memory into a plurality of registers. The method further includes the step of maintaining a table that lists each register of the plurality of registers and that indicates when data has been loaded into each register by the executing load multiple instruction. The method concludes by executing an instruction that is dependent upon source operand data loaded by the load multiple instruction into a register of the plurality of registers indicated by the instruction as a source register, prior to the load multiple instruction completing its execution, when the table indicates the source operand data has been loaded into the source register. Also, according to the present invention, a method of executing a store multiple instruction in a superscaler microprocessor is provided. This method comprises the steps of dispatching a store multiple instruction to a load/store unit, whereupon the load/store unit begins executing the store multiple instruction, wherein the load store instruction stores data from a plurality of registers to memory; and executing a fixed point instruction that is dependent upon data being stored by the store multiple instruction from a register of the plurality of registers indicated by the fixed point instruction as a source register, prior to the store multiple instruction completing its execution, but prohibiting the executing fixed point instruction from writing to a register of the plurality of registers prior to the store multiple instruction completing.
摘要翻译： 提供了一种在超标量微处理器中执行加载多指令的方法和装置。 该方法包括以下步骤：向加载/存储单元发送加载多个指令，其中加载/存储单元开始执行分派的加载多个指令，并且其中加载多个指令将数据从存储器加载到多个寄存器中。 该方法还包括维护列出多个寄存器的每个寄存器并且通过执行加载多个指令指示何时将数据加载到每个寄存器中的表的步骤。 该方法通过在载入多个指令完成其执行之前执行依赖于由加载多个指令加载的源操作数数据到由指令指示的多个寄存器的寄存器中作为源寄存器的指令，当该表 表示源操作数数据已加载到源寄存器中。 此外，根据本发明，提供了一种在超标量微处理器中执行存储多重指令的方法。 该方法包括以下步骤：将存储多重指令分派到加载/存储单元，从而加载/存储单元开始执行存储多指令，其中加载存储指令将数据从多个寄存器存储到存储器; 并且在存储多个指令完成其执行之前，执行依赖于由所述固定点指令指示的多个寄存器的寄存器作为源寄存器的存储多个指令存储的数据的固定点指令，但是禁止 在存储多个指令完成之前，从写入到多个寄存器的寄存器执行固定点指令。
-
公开(公告)号：US5694565A
公开(公告)日：1997-12-02
申请号：US526343
申请日：1995-09-11
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3834 , G06F9/3838
摘要： A method and device of executing a load multiple instruction in a superscaler microprocessor is provided. The method comprises the steps of dispatching a load multiple instruction to a load/store unit, wherein the load/store unit begins execution of a dispatched load multiple instruction, and wherein the load multiple instruction loads data from memory into a plurality of registers. The method further includes the step of maintaining a table that lists each register of the plurality of registers and that indicates when data has been loaded into each register by the executing load multiple instruction. The method concludes by executing an instruction that is dependent upon source operand data loaded by the load multiple instruction into a register of the plurality of registers indicated by the instruction as a source register, prior to the load multiple instruction completing its execution, when the table indicates the source operand data has been loaded into the source register. Also, according to the present invention, a method of executing a store multiple instruction in a superscaler microprocessor is provided. This method comprises the steps of dispatching a store multiple instruction to a load/store unit, whereupon the load/store unit begins executing the store multiple instruction, wherein the load store instruction stores data from a plurality of registers to memory; and executing a fixed point instruction that is dependent upon data being stored by the store multiple instruction from a register of the plurality of registers indicated by the fixed point instruction as a source register, prior to the store multiple instruction completing its execution, but prohibiting the executing fixed point instruction from writing to a register of the plurality of registers prior to the store multiple instruction completing.
-
公开(公告)号：US20060294356A1
公开(公告)日：2006-12-28
申请号：US11168757
申请日：2005-06-27
IPC分类号： G06F9/00
CPC分类号： G06F9/44573
摘要： Apparatuses and methods of an executable-in-place solid-state device are disclosed. In one embodiment, a solid-state device includes a flash memory coupled to a dynamic random access memory, the dynamic random access memory to store at least as much data as the flash memory; and a logic circuit coupled to the flash memory and the dynamic access memory to copy data from the flash memory to the dynamic random access memory on power up of a data processing system coupled to the solid-state device. The logic circuit is to minimize writes to the flash memory by using the dynamic access memory as a working memory during operation of the data processing system, and/or to block at least some sectors of at least one of the flash memory and the dynamic random access memory when the data processing system uses the working memory to conserve power usage of the solid-state device.
摘要翻译： 公开了可执行就地固态设备的装置和方法。 在一个实施例中，固态设备包括耦合到动态随机存取存储器的闪速存储器，动态随机存取存储器至少存储与闪速存储器相同的数据; 以及耦合到闪速存储器和动态访问存储器的逻辑电路，用于在耦合到固态设备的数据处理系统上电时将数据从闪速存储器复制到动态随机存取存储器。 逻辑电路是通过在数据处理系统的操作期间使用动态存取存储器作为工作存储器来最小化对闪速存储器的写入，和/或阻止闪存和动态随机的至少一个的至少一些扇区 当数据处理系统使用工作存储器来节省固态设备的功率使用时，存取存储器。
-
17.发明授权Method and system for executing a program within a multiscalar processor by processing linked thread descriptors 失效通过处理链接线程描述符来执行多级数据处理器内程序的方法和系统公开(公告)号：US06212542B1
公开(公告)日：2001-04-03
申请号：US08767487
申请日：1996-12-16
IPC分类号： G06F900
CPC分类号： G06F9/4843 , G06F9/30087 , G06F9/3009 , G06F9/3851
摘要： A multiscalar processor and method of executing a multiscalar program within a multiscalar processor having a plurality of processing elements and a thread scheduler are provided. The multiscalar program includes a plurality of threads that are each composed of one or more instructions of a selected instruction set architecture. Each of the plurality of threads has a single entry point and a plurality of possible exit points. The multiscalar program further comprises thread code including a plurality of data structures that are each associated with a respective one of the plurality of threads. According to the method, a third data structure among the plurality of data structures is supplied to the thread scheduler. The third data structure, which is associated with a third thread among the plurality of threads, specifies a first data structure associated with a first possible exit point of the third thread and a second data structure associated with a second possible exit point of the third thread. The third thread is assigned to a selected one of the plurality of processing elements for execution. Prior to completing execution of the third thread, the thread scheduler selects from among the first and the second possible exit points of the third thread. In response to the selection, a corresponding one of the first and second data structures is loaded into the thread scheduler for processing.
摘要翻译： 提供了一种在具有多个处理元件和线程调度器的多级数值处理器内执行多级计算机的多级数据处理器和方法。 多节目程序包括多个线程，每个线程由所选择的指令集架构的一个或多个指令组成。 多个线程中的每一个具有单个入口点和多个可能的出口点。 多节目程序还包括线程代码，其包括多个数据结构，每个数据结构与多个线程中的相应一个线程相关联。 根据该方法，将多个数据结构中的第三数据结构提供给线程调度器。 与多个线程中的第三线程相关联的第三数据结构指定与第三线程的第一可能退出点相关联的第一数据结构和与第三线程的第二可能出口点相关联的第二数据结构 。 第三线程被分配给用于执行的多个处理元件中的所选择的一个。 在完成第三线程的执行之前，线程调度器从第三线程的第一和第二可能出口点中选择。 响应于该选择，第一和第二数据结构中相应的一个被加载到线程调度器中进行处理。
-
18.发明授权Method and system for constructing a program including out-of-order threads and processor and method for executing threads out-of-order 失效用于构建包括无序线程和处理器的程序的方法和系统以及执行无序线程的方法
公开(公告)号：US5913925A
公开(公告)日：1999-06-22
申请号：US767490
申请日：1996-12-16
CPC分类号： G06F9/4843 , G06F9/44
摘要： A method and system for constructing a program are provided. According to the method, each of a plurality of instructions are assigned to at least one of a plurality of threads. The plurality of threads include first, second, and third threads, where the third thread follows the first thread and precedes the second thread in a logical program order. A data structure associated with the first thread is then constructed. The data structure includes an indication that execution of the second thread is to be initiated prior to initiation of execution of the third thread. According to one embodiment, the indication within the data structure is a pointer that specifies a second data structure associated with the second thread.
摘要翻译： 提供了一种用于构建程序的方法和系统。 根据该方法，将多个指令中的每一个分配给多个线程中的至少一个。 多个线程包括第一，第二和第三线程，其中第三线程遵循第一线程并且以逻辑程序顺序在第二线程之前。 然后构建与第一线程相关联的数据结构。 数据结构包括在开始执行第三线程之前要启动第二线程的执行的指示。 根据一个实施例，数据结构内的指示是指定与第二线程相关联的第二数据结构的指针。
-
19.发明授权Method and system for constructing a program including a navigation instruction 失效用于构建包括导航指令的程序的方法和系统
公开(公告)号：US5887166A
公开(公告)日：1999-03-23
申请号：US767491
申请日：1996-12-16
CPC分类号： G06F9/4881
摘要： A method and system are provided for constructing a program executable by a processor including one or more processing elements for executing threads and a thread scheduler for assigning threads to the processing elements for execution. According to the method, a plurality of threads are provided that each include at least one control flow instruction. From one or more control flow instructions within the plurality of threads, a condition upon which execution of a particular thread depends is determined. In response to the determination, at least one navigation instruction executable by the thread scheduler is created that indicates that the particular thread is to be assigned to one of the processing elements for execution in response to the condition.
摘要翻译： 提供了一种方法和系统，用于构建可由包括用于执行线程的一个或多个处理元件和用于将线程分配给处理元件以执行的线程调度器的处理器执行的程序。 根据该方法，提供多个线程，每个线程包括至少一个控制流程指令。 从多个线程内的一个或多个控制流程指令，确定特定线程的执行所依赖的状态。 响应于该确定，创建可由线程调度器执行的至少一个导航指令，其指示将特定线程分配给响应于条件执行的一个处理元件。
-
20.发明授权Method and apparatus for dynamic allocation of registers for intermediate floating-point results 失效用于中间浮点数结果的寄存器的动态分配方法和装置
公开(公告)号：US5805916A
公开(公告)日：1998-09-08
申请号：US758017
申请日：1996-11-27
CPC分类号： G06F9/30014 , G06F9/30105 , G06F9/30112 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3875
摘要： The present invention relates to a multiple stage execution unit for executing instructions in a microprocessor having a plurality of rename registers for storing execution results, an instruction cache for storing instructions, each instruction being associated with a rename register, a sequencer unit for providing an instruction to the execution unit, and a data cache for providing data to the execution unit. In one version, the execution unit includes a first stage which generates an intermediate result from the data according to an instruction; a means for providing a first portion of the intermediate result to an intermediate register; a means for providing a second portion of the intermediate result to a rename register associated with the instruction; a means for passing the first portion from the intermediate register to a second stage of the execution unit; a means for passing the second portion from the rename register to the second stage of the execution unit; wherein the second stage of the execution unit operates on the first and second portions according to the instruction.
摘要翻译： 本发明涉及一种多级执行单元，用于在微处理器中执行指令，该微处理器具有用于存储执行结果的多个重命名寄存器，用于存储指令的指令高速缓存，每个指令与重命名寄存器相关联，定序器单元用于提供指令 以及用于向执行单元提供数据的数据高速缓存。 在一个版本中，执行单元包括根据指令从数据生成中间结果的第一阶段; 用于将中间结果的第一部分提供给中间寄存器的装置; 用于将中间结果的第二部分提供给与指令相关联的重命名寄存器的装置; 用于将第一部分从中间寄存器传递到执行单元的第二级的装置; 用于将第二部分从重命名寄存器传递到执行单元的第二级的装置; 其中执行单元的第二级根据该指令在第一和第二部分上操作。
-
-
-
-
-
-
-
-
-
搜索结果
48 条记录 (耗时 0.042 秒)
