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1.发明授权
公开(公告)号：US5867684A
公开(公告)日：1999-02-02
申请号：US873013
申请日：1997-06-11
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3834 , G06F9/3838
摘要： A method and device of executing a load multiple instruction in a superscaler microprocessor is provided. The method comprises the steps of dispatching a load multiple instruction to a load/store unit, wherein the load/store unit begins execution of a dispatched load multiple instruction, and wherein the load multiple instruction loads data from memory into a plurality of registers. The method further includes the step of maintaining a table that lists each register of the plurality of registers and that indicates when data has been loaded into each register by the executing load multiple instruction. The method concludes by executing an instruction that is dependent upon source operand data loaded by the load multiple instruction into a register of the plurality of registers indicated by the instruction as a source register, prior to the load multiple instruction completing its execution, when the table indicates the source operand data has been loaded into the source register. Also, according to the present invention, a method of executing a store multiple instruction in a superscaler microprocessor is provided. This method comprises the steps of dispatching a store multiple instruction to a load/store unit, whereupon the load/store unit begins executing the store multiple instruction, wherein the load store instruction stores data from a plurality of registers to memory; and executing a fixed point instruction that is dependent upon data being stored by the store multiple instruction from a register of the plurality of registers indicated by the fixed point instruction as a source register, prior to the store multiple instruction completing its execution, but prohibiting the executing fixed point instruction from writing to a register of the plurality of registers prior to the store multiple instruction completing.
摘要翻译： 提供了一种在超标量微处理器中执行加载多指令的方法和装置。 该方法包括以下步骤：向加载/存储单元发送加载多个指令，其中加载/存储单元开始执行分派的加载多个指令，并且其中加载多个指令将数据从存储器加载到多个寄存器中。 该方法还包括维护列出多个寄存器的每个寄存器并且通过执行加载多个指令指示何时将数据加载到每个寄存器中的表的步骤。 该方法通过在载入多个指令完成其执行之前执行依赖于由加载多个指令加载的源操作数数据到由指令指示的多个寄存器的寄存器中作为源寄存器的指令，当该表 表示源操作数数据已加载到源寄存器中。 此外，根据本发明，提供了一种在超标量微处理器中执行存储多重指令的方法。 该方法包括以下步骤：将存储多重指令分派到加载/存储单元，从而加载/存储单元开始执行存储多指令，其中加载存储指令将数据从多个寄存器存储到存储器; 并且在存储多个指令完成其执行之前，执行依赖于由所述固定点指令指示的多个寄存器的寄存器作为源寄存器的存储多个指令存储的数据的固定点指令，但是禁止 在存储多个指令完成之前，从写入到多个寄存器的寄存器执行固定点指令。
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公开(公告)号：US5694565A
公开(公告)日：1997-12-02
申请号：US526343
申请日：1995-09-11
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3834 , G06F9/3838
摘要： A method and device of executing a load multiple instruction in a superscaler microprocessor is provided. The method comprises the steps of dispatching a load multiple instruction to a load/store unit, wherein the load/store unit begins execution of a dispatched load multiple instruction, and wherein the load multiple instruction loads data from memory into a plurality of registers. The method further includes the step of maintaining a table that lists each register of the plurality of registers and that indicates when data has been loaded into each register by the executing load multiple instruction. The method concludes by executing an instruction that is dependent upon source operand data loaded by the load multiple instruction into a register of the plurality of registers indicated by the instruction as a source register, prior to the load multiple instruction completing its execution, when the table indicates the source operand data has been loaded into the source register. Also, according to the present invention, a method of executing a store multiple instruction in a superscaler microprocessor is provided. This method comprises the steps of dispatching a store multiple instruction to a load/store unit, whereupon the load/store unit begins executing the store multiple instruction, wherein the load store instruction stores data from a plurality of registers to memory; and executing a fixed point instruction that is dependent upon data being stored by the store multiple instruction from a register of the plurality of registers indicated by the fixed point instruction as a source register, prior to the store multiple instruction completing its execution, but prohibiting the executing fixed point instruction from writing to a register of the plurality of registers prior to the store multiple instruction completing.
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3.发明授权Processor and method for out-of-order completion of floating-point operations during load/store multiple operations 失效用于在加载/存储多个操作期间浮点运算的无序完成的处理器和方法
公开(公告)号：US5850563A
公开(公告)日：1998-12-15
申请号：US526610
申请日：1995-09-11
申请人： Albert J. Loper , Soummya Mallick
发明人： Albert J. Loper , Soummya Mallick
CPC分类号： G06F9/30043 , G06F9/3838 , G06F9/3863
摘要： A method and apparatus in a superscalar microprocessor for early completion of floating-point instructions prior to a previous load/store multiple instruction is provided. The microprocessor's load/store execution unit loads or stores data to or from the general purpose registers, and the microprocessor's dispatch unit dispatches instructions to a plurality of execution units, including the load/store execution unit and the floating point execution unit. The method comprises the dispatch unit dispatching a multi-register instruction to the load/store unit to begin execution of the multi-register instruction, wherein the multi-register instruction, such as a store multiple or a load multiple, stores or loads data from more than one of the plurality of general purpose registers to memory, and further, prior to the multi-register instruction finishing execution in the load/store unit, the dispatch unit dispatches a floating-point instruction, which is dependent upon source operand data stored in one or more floating-point registers of the plurality of floating point registers, to the floating-point execution unit, wherein the dispatched floating-point instruction completes execution prior to the multi-register instruction finishing execution.
摘要翻译： 提供了在先前加载/存储多个指令之前的超标量微处理器中用于早期完成浮点指令的方法和装置。 微处理器的加载/存储执行单元向通用寄存器加载或存储数据，微处理器的调度单元将指令分派到包括加载/存储执行单元和浮点执行单元的多个执行单元。 该方法包括：调度单元向加载/存储单元分配多寄存器指令以开始执行多寄存器指令，其中多寄存器指令（例如存储器多个或加载倍数）存储或加载来自 多个通用寄存器中的多于一个存储器，此外，在多个寄存器指令在加载/存储单元中完成执行之前，调度单元调度浮点指令，其依赖于存储的源操作数据 在多个浮点寄存器的一个或多个浮点寄存器中，提供给浮点执行单元，其中调度浮点指令在多寄存器指令完成执行之前完成执行。
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4.发明授权Method and system for recoding noneffective instructions within a data processing system 失效在数据处理系统内重新编码无效指令的方法和系统
公开(公告)号：US5619408A
公开(公告)日：1997-04-08
申请号：US387145
申请日：1995-02-10
申请人： Bryan Black , Marvin A. Denman , Lee E. Eisen , Robert T. Golla , Albert J. Loper, Jr. , Soummya Mallick , Russell A. Reininger
发明人： Bryan Black , Marvin A. Denman , Lee E. Eisen , Robert T. Golla , Albert J. Loper, Jr. , Soummya Mallick , Russell A. Reininger
CPC分类号： G06F9/3017 , G06F9/30145
摘要： A method and system are disclosed for processing instructions within a data processing system including a processor having a plurality of execution units. According to the method of the present invention, a number of instructions stored within a memory within the data processing system are retrieved from memory. A selected instruction among the number of instructions is decoded to determine if the selected instruction would be noneffective if executed by the processor. In a preferred embodiment of the present invention, noneffective instructions include instructions with invalid opcodes and instructions that would not change the value of any data register within the processor. In response to determining that the selected instruction would be noneffective if executed by the processor, the selected instruction is recoded into a specified instruction format prior to dispatching the selected instruction to one of the number of execution units. Detecting noneffective instructions prior to dispatch reduces the decode logic required within the dispatcher and enhances processor performance.
摘要翻译： 公开了一种用于处理包括具有多个执行单元的处理器的数据处理系统内的指令的方法和系统。 根据本发明的方法，从存储器中检索存储在数据处理系统内的存储器内的多个指令。 解码指令数目中的选择指令，以确定所选择的指令是否由处理器执行时是无效的。 在本发明的优选实施例中，无效指令包括具有无效操作码的指令和不会改变处理器内的任何数据寄存器的值的指令。 响应于确定所选择的指令如果由处理器执行将是无效的，则在将所选择的指令分派到多个执行单元之一之前，所选择的指令被重新编码为指定的指令格式。 在调度之前检测无效指令可减少调度程序中所需的解码逻辑，并提高处理器的性能。
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5.发明授权Method and system for selective support of non-architected instructions within a superscaler processor system utilizing a special access bit within a machine state register 失效在利用机器状态寄存器内的特殊访问位的超标量处理器系统内选择性地支持非架构指令的方法和系统
公开(公告)号：US5758141A
公开(公告)日：1998-05-26
申请号：US386977
申请日：1995-02-10
CPC分类号： G06F9/30181 , G06F9/30145 , G06F9/30189 , G06F9/45554
摘要： A method and system for permitting the selective support of non-architected instructions within a superscalar processor system. A special access bit within the system machine state register is provided and set in response to each initiation of an application during which execution of non-architected instructions is desired. Thereafter, each time a non-architected instruction is decoded the status of the special access bit is determined. The non-architected instruction is executed in response to a set state of the special access bit. The illegal instruction program interrupt is issued in response to an attempted execution of a non-architected instruction if the special access bit is not set. In this manner, for example, complex instruction set computing (CISC) instructions may be selectively enabled for execution within a reduced instruction set computing (RISC) data processing system while maintaining full architectural compliance with the reduced instruction set computing (RISC) instructions.
摘要翻译： 一种用于允许在超标量处理器系统内选择性地支持非架构指令的方法和系统。 系统机器状态寄存器内的特殊访问位被提供和设置为响应于期望执行非架构指令的应用程序的每个启动。 此后，每当非架构化指令被解码时，确定特殊访问位的状态。 响应于特殊访问位的设置状态执行非架构指令。 如果未设置特殊访问位，则响应于非架构化指令的尝试执行而发出非法指令程序中断。 以这种方式，例如，复杂指令集计算（CISC）指令可以选择性地启用以在精简指令集计算（RISC）数据处理系统中执行，同时保持与精简指令集计算（RISC）指令的完全架构符合性。
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6.发明授权Method and system for recording noneffective instructions within a data processing system 失效在数据处理系统中记录无效指令的方法和系统
公开(公告)号：US5717587A
公开(公告)日：1998-02-10
申请号：US649753
申请日：1996-05-15
申请人： Bryan Black , Marvin A. Denman , Lee E. Eisen , Robert T. Golla , Albert J. Loper, Jr. , Soummya Mallick , Russell Adley Reininger
发明人： Bryan Black , Marvin A. Denman , Lee E. Eisen , Robert T. Golla , Albert J. Loper, Jr. , Soummya Mallick , Russell Adley Reininger
CPC分类号： G06F9/3017 , G06F9/30145
摘要： A method and system are disclosed for processing instructions within a data processing system including a processor having a plurality of execution units. According to the method of the present invention, a number of instructions stored within a memory within the data processing system are retrieved from memory. A selected instruction among the number of instructions is decoded to determine if the selected instruction would be noneffective if executed by the processor. In a preferred embodiment of the present invention, noneffective instructions include instructions with invalid opcodes and instructions that would not change the value of any data register within the processor. In response to determining that the selected instruction would be noneffective if executed by the processor, the selected instruction is recoded into a specified instruction format prior to dispatching the selected instruction to one of the number of execution units. Detecting noneffective instructions prior to dispatch reduces the decode logic required within the dispatcher and enhances processor performance.
摘要翻译： 公开了一种用于处理包括具有多个执行单元的处理器的数据处理系统内的指令的方法和系统。 根据本发明的方法，从存储器中检索存储在数据处理系统内的存储器内的多个指令。 解码指令数目中的选择指令，以确定所选择的指令是否由处理器执行时是无效的。 在本发明的优选实施例中，无效指令包括具有无效操作码的指令和不会改变处理器内的任何数据寄存器的值的指令。 响应于确定所选择的指令如果由处理器执行将是无效的，则在将所选择的指令分派到多个执行单元之一之前，所选择的指令被重新编码为指定的指令格式。 在调度之前检测无效指令可减少调度程序中所需的解码逻辑，并提高处理器的性能。
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7.发明授权Method for executing speculative load instructions in high-performance processors 失效在高性能处理器中执行推测加载指令的方法
公开(公告)号：US5611063A
公开(公告)日：1997-03-11
申请号：US597647
申请日：1996-02-06
CPC分类号： G06F9/30043 , G06F9/383 , G06F9/3842
摘要： A method for selectively executing speculative load instructions in a high-performance processor is disclosed. In accordance with the present disclosure, when a speculative load instruction for which the data is not stored in a data cache is encountered, a bit within an enable speculative load table which is associated with that particular speculative load instruction is read in order to determine a state of the bit. If the associated bit is in a first state, data for the speculative load instruction is requested from a system bus and further execution of the speculative load instruction is then suspended to wait for control signals from a branch processing unit. If the associated bit is in a second state, the execution of the speculative load instruction is immediately suspended to wait for control signals from the branch processing unit. If the speculative load instruction is executed in response to the control signals, then the associated bit in the enable speculative load table will be set to the first state. However, if the speculative load instruction is not executed in response to the control signals, then the associated bit in the enable speculative load table is set to the second state. In this manner, the displacement of useful data in the data cache due to wrongful execution of the speculative load instruction is avoided.
摘要翻译： 公开了一种用于选择性地执行高性能处理器中的推测性加载指令的方法。 根据本公开，当遇到数据未被存储在数据高速缓冲存储器中的推测性加载指令时，读取与该特定推测加载指令相关联的使能投机载入表中的位，以便确定 状态的位。 如果关联位处于第一状态，则从系统总线请求用于推测加载指令的数据，然后暂停推测加载指令的进一步执行，以等待来自分支处理单元的控制信号。 如果相关联的位处于第二状态，则推测加载指令的执行被立即停止，以等待来自分支处理单元的控制信号。 如果响应于控制信号执行推测加载指令，则使能推测加载表中的关联位将被设置为第一状态。 然而，如果不响应于控制信号执行推测加载指令，则使能推测负载表中的关联位被设置为第二状态。 以这种方式，避免了由于推测加载指令的错误执行而在数据高速缓存中的有用数据的位移。
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8.发明授权Method and system for enhanced management operation utilizing intermixed user level and supervisory level instructions with partial concept synchronization 失效利用混合用户级别和部分概念同步的监督级别指令来增强管理操作的方法和系统
公开(公告)号：US5764969A
公开(公告)日：1998-06-09
申请号：US387149
申请日：1995-02-10
CPC分类号： G06F9/461 , G06F12/1475
摘要： A method and system for enhanced system management operations in a superscalar data processing system. Those supervisory level instructions which execute selected privileged operations within protected memory space are first identified as not requiring a full context synchronization. Each time execution of such an instruction is initiated an enable special access (ESA) instruction is executed as an entry point to that instruction or group of instructions. A portion of the machine state register for the data processing system is stored and the machine state register is then modified as follows: a problem bit is set, changing the execution privilege state to "supervisor;" external interrupts are disabled; and access privilege state bit is set; and, a special access mode bit is set, allowing execution of special instructions. The instructions which execute the selected privileged operations within the protected memory space are then executed. A disable special access (DSA) instruction is then executed which restores the bits within the machine state register which were modified during the ESA instruction. The ESA and DSA instructions are implemented without modifying the instruction stream by utilizing user level procedure calls, thereby reducing the overhead of the branch table necessary to determine the desired execution path.
摘要翻译： 一种用于在超标量数据处理系统中增强系统管理操作的方法和系统。 在受保护的存储器空间内执行所选特权操作的这些监督级指令首先被识别为不需要完整的上下文同步。 每次执行这样的指令时，执行使能特殊访问（ESA）指令作为该指令或指令组的入口点。 存储用于数据处理系统的机器状态寄存器的一部分，然后如下修改机器状态寄存器：设置问题位，将执行特权状态改变为“主管”; 外部中断被禁用; 并设置访问权限状态位; 并设置特殊访问模式位，允许执行特殊指令。 然后执行在受保护的存储器空间内执行所选择的特权操作的指令。 然后执行禁用特殊访问（DSA）指令，其恢复机器状态寄存器中在ESA指令期间被修改的位。 通过利用用户级过程调用来实现ESA和DSA指令而不修改指令流，从而减少确定所需执行路径所需的分支表的开销。
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9.发明授权Method and system for executing a program within a multiscalar processor by processing linked thread descriptors 失效通过处理链接线程描述符来执行多级数据处理器内程序的方法和系统公开(公告)号：US06212542B1
公开(公告)日：2001-04-03
申请号：US08767487
申请日：1996-12-16
IPC分类号： G06F900
CPC分类号： G06F9/4843 , G06F9/30087 , G06F9/3009 , G06F9/3851
摘要： A multiscalar processor and method of executing a multiscalar program within a multiscalar processor having a plurality of processing elements and a thread scheduler are provided. The multiscalar program includes a plurality of threads that are each composed of one or more instructions of a selected instruction set architecture. Each of the plurality of threads has a single entry point and a plurality of possible exit points. The multiscalar program further comprises thread code including a plurality of data structures that are each associated with a respective one of the plurality of threads. According to the method, a third data structure among the plurality of data structures is supplied to the thread scheduler. The third data structure, which is associated with a third thread among the plurality of threads, specifies a first data structure associated with a first possible exit point of the third thread and a second data structure associated with a second possible exit point of the third thread. The third thread is assigned to a selected one of the plurality of processing elements for execution. Prior to completing execution of the third thread, the thread scheduler selects from among the first and the second possible exit points of the third thread. In response to the selection, a corresponding one of the first and second data structures is loaded into the thread scheduler for processing.
摘要翻译： 提供了一种在具有多个处理元件和线程调度器的多级数值处理器内执行多级计算机的多级数据处理器和方法。 多节目程序包括多个线程，每个线程由所选择的指令集架构的一个或多个指令组成。 多个线程中的每一个具有单个入口点和多个可能的出口点。 多节目程序还包括线程代码，其包括多个数据结构，每个数据结构与多个线程中的相应一个线程相关联。 根据该方法，将多个数据结构中的第三数据结构提供给线程调度器。 与多个线程中的第三线程相关联的第三数据结构指定与第三线程的第一可能退出点相关联的第一数据结构和与第三线程的第二可能出口点相关联的第二数据结构 。 第三线程被分配给用于执行的多个处理元件中的所选择的一个。 在完成第三线程的执行之前，线程调度器从第三线程的第一和第二可能出口点中选择。 响应于该选择，第一和第二数据结构中相应的一个被加载到线程调度器中进行处理。
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10.发明授权Method and system for constructing a program including out-of-order threads and processor and method for executing threads out-of-order 失效用于构建包括无序线程和处理器的程序的方法和系统以及执行无序线程的方法
公开(公告)号：US5913925A
公开(公告)日：1999-06-22
申请号：US767490
申请日：1996-12-16
CPC分类号： G06F9/4843 , G06F9/44
摘要： A method and system for constructing a program are provided. According to the method, each of a plurality of instructions are assigned to at least one of a plurality of threads. The plurality of threads include first, second, and third threads, where the third thread follows the first thread and precedes the second thread in a logical program order. A data structure associated with the first thread is then constructed. The data structure includes an indication that execution of the second thread is to be initiated prior to initiation of execution of the third thread. According to one embodiment, the indication within the data structure is a pointer that specifies a second data structure associated with the second thread.
摘要翻译： 提供了一种用于构建程序的方法和系统。 根据该方法，将多个指令中的每一个分配给多个线程中的至少一个。 多个线程包括第一，第二和第三线程，其中第三线程遵循第一线程并且以逻辑程序顺序在第二线程之前。 然后构建与第一线程相关联的数据结构。 数据结构包括在开始执行第三线程之前要启动第二线程的执行的指示。 根据一个实施例，数据结构内的指示是指定与第二线程相关联的第二数据结构的指针。
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