公开(公告)号：US08334588B2

公开(公告)日：2012-12-18

申请号：US13098340

申请日：2011-04-29

Applicant: Jin-Yuan Lee ,  Eric Lin

Inventor： Jin-Yuan Lee ,  Eric Lin

IPC: H01L23/48

CPC classification number: H01L24/12 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02335 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A circuit component comprising a substrate, and a conductive layer over the substrate, wherein the conductive layer comprises a first portion between a first opening in the conductive layer and a second opening in the conductive layer, wherein the first and second openings are enclosed by the conductive layer, wherein a void is over the substrate and under the conductive layer, wherein the first portion and the first and second openings are over the void.

Abstract translation: 一种电路部件，包括衬底和在衬底上的导电层，其中导电层包括在导电层中的第一开口和导电层中的第二开口之间的第一部分，其中第一和第二开口由 导电层，其中空隙在所述衬底上并在所述导电层下方，其中所述第一部分和所述第一和第二开口在所述空隙上方。

公开(公告)号：US07265045B2

公开(公告)日：2007-09-04

申请号：US10925302

申请日：2004-08-24

Applicant: Jin-Yuan Lee ,  Eric Lin

Inventor： Jin-Yuan Lee ,  Eric Lin

IPC: H01L21/44

CPC classification number: H01L24/12 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02335 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A new method to form an integrated circuit device is achieved. The method comprises providing a substrate. A sacrificial layer is formed overlying the substrate. The sacrificial layer is patterned to form temporary vertical spacers where conductive bonding locations are planned. A conductive layer is deposited overlying the temporary vertical spacers and the substrate. The conductive layer is patterned to form conductive bonding locations overlying the temporary vertical spacers. The temporary vertical spacers are etched away to create voids underlying the conductive bonding locations.

Abstract translation: 实现了形成集成电路器件的新方法。 该方法包括提供基底。 覆盖衬底上形成牺牲层。 将牺牲层图案化以形成临时的垂直间隔件，其中计划导电接合位置。 沉积在临时垂直间隔物和基底上的导电层。 将导电层图案化以形成覆盖临时垂直间隔物的导电接合位置。 蚀刻掉临时的垂直间隔物以在导电接合位置下方产生空隙。

公开(公告)号：US20060017673A1

公开(公告)日：2006-01-26

申请号：US10938532

申请日：2004-09-13

Applicant: Brian Chen ,  Eric Lin

Inventor： Brian Chen ,  Eric Lin

IPC: G09G3/36

CPC classification number: G06F1/1616 ,  G06F1/1652 ,  G06F1/1656 ,  G06F1/1698

Abstract: The present invention provides a display device, comprising: an input unit, for inputting a data; a storage unit, for storing the input data; an output unit, for displaying the data; a control unit, electrically connected to the input unit, the output unit and the storage unit for controlling the same; a power supply, electrically connected to the input unit, the output unit and the storage unit for providing power to the same; and a housing; wherein the input unit, the output unit, the storage unit, the control unit and the power supply are arranged inside an accommodation space of the housing. In addition, the output unit can be a flexible paper-like display.

Abstract translation: 本发明提供了一种显示装置，包括：输入单元，用于输入数据; 存储单元，用于存储输入数据; 输出单元，用于显示数据; 电连接到输入单元的控制单元，用于控制单元的输出单元和存储单元; 电连接到输入单元，输出单元和存储单元，用于向其提供电力; 和房屋; 其中所述输入单元，所述输出单元，所述存储单元，所述控制单元和所述电源被布置在所述壳体的容纳空间的内部。 此外，输出单元可以是柔性的纸状显示器。

公开(公告)号：US20060002386A1

公开(公告)日：2006-01-05

申请号：US10881226

申请日：2004-06-30

Applicant: James Yik ,  Rong-Feng Chang ,  Eric Lin ,  John Ta ,  Craig Barrack

Inventor： James Yik ,  Rong-Feng Chang ,  Eric Lin ,  John Ta ,  Craig Barrack

IPC: H04L12/56

CPC classification number: H04L49/3063 ,  H04L49/201 ,  H04L49/602

Abstract: A packet switching node having a pipelined packet processing architecture processing packets received via an input port associated with the packet switching node is presented. The method performed by the apparatus includes: determining a packet frame type of the packet received; selectively extracting packet header field values specific to a packet frame type, the extracted packet header field value including packet addressing information; ascribing to the packet a preliminary action to be performed in respect of the packet; searching packet switching information tracked by the packet switching node based on extracted packet addressing information; formulating a preliminary switch response for the packet; classifying the packet into one of a plurality of packet flows; modifying the preliminary switch response in accordance with one of the preliminary action, the packet flow into which the packet was classified, and a default port action corresponding to the input port; modifying the packet header in accordance with one of the preliminary action, the packet flow, and the default port action; and processing the packet in accordance with the switch response. Advantages are derived from: pipelined processing of packets which enables short-cutting the rest of the processing for improper packets; a flexible frame type determination which is fast for well know frame types yet flexible in support of new frame types delaying obsolescence of a particular implementation; an early determination of a processing action which is successively refined by subsequent stages; a combined Layer-2 and Layer-3 network addressing search engine operating on short bit length indexed Layer-2 and Layer-3 network addresses reducing network address table storage requirements, requiring a reduced data transfer bandwidth for network address table access, a large external hashed primary network address table, and a small internal secondary network address table; an early determination of a switch response; and packet-classification-based switch response and packet header modification.

公开(公告)号：US20060002292A1

公开(公告)日：2006-01-05

申请号：US10903437

申请日：2004-07-30

Applicant: Rong-Feng Chang ,  Eric Lin ,  Craig Barrack

Inventor： Rong-Feng Chang ,  Eric Lin ,  Craig Barrack

IPC: H04L1/00

CPC classification number: H04L12/462 ,  H04L43/10 ,  H04L45/02 ,  H04L45/22 ,  H04L45/28

Abstract: A hardware-based failover scheme enabling rapid end-to-end recovery is provided. Hardware logic periodically generates, transmits, receives, and processes heartbeat packets, sent from one end of the communications network to another, and then returned back. If a communications network node or communications link failure is being experienced along the transport path, then the hardware logic rapidly swaps the affected traffic conveyed to a pre-established backup transport path, typically within microseconds. Advantages are derived from the rapid failover effected end-to-end which enables continued delivery of provisioned communications services improving the resiliency and/or availability of a communications network.

Abstract translation: 提供了基于硬件的故障转移方案，实现快速的端到端恢复。 硬件逻辑周期性地生成，发送，接收和处理从通信网络的一端发送到另一端的心跳信息包，然后返回。 如果沿着传输路径遇到通信网络节点或通信链路故障，则硬件逻辑快速地将传送到预先建立的备份传输路径的受影响的业务交换，通常在微秒内。 优点来源于端对端的快速故障转移，从而能够持续提供所提供的通信服务，从而提高通信网络的弹性和/或可用性。

公开(公告)号：USD467440S1

公开(公告)日：2002-12-24

申请号：US29158126

申请日：2002-03-28

Applicant: Glenn Lindaman ,  Eric Lin

Designer： Glenn Lindaman ,  Eric Lin

公开(公告)号：US08015557B2

公开(公告)日：2011-09-06

申请号：US12613295

申请日：2009-11-05

Applicant: Miaobo Chen ,  Qi Zhang ,  Eric Lin ,  Jianhui Li ,  Yun Wang

Inventor： Miaobo Chen ,  Qi Zhang ,  Eric Lin ,  Jianhui Li ,  Yun Wang

IPC: G06F9/44

CPC classification number: G06F9/45516

Abstract: Methods and apparatus to support the execution of a managed application that is linked to a native library or application are disclosed. The disclosed methods and apparatus support a virtual machine that is associated with the same ISA as the executing platform, while the ISA of the native library or application is of a different ISA. The disclosed methods and apparatus also support the execution of a managed application that is linked with several native libraries or applications that are associated with several different ISAs respectively.

Abstract translation: 公开了支持与本地库或应用相关联的被管理应用的执行的方法和装置。 所公开的方法和装置支持与执行平台相同的ISA相关联的虚拟机，而本地库或应用的ISA是不同的ISA。 所公开的方法和装置还支持与分别与若干不同的ISA相关联的几个本地库或应用链接的被管理应用的执行。

公开(公告)号：US07813263B2

公开(公告)日：2010-10-12

申请号：US10903437

申请日：2004-07-30

Applicant: Rong-Feng Chang ,  Eric Lin ,  Craig Barrack

Inventor： Rong-Feng Chang ,  Eric Lin ,  Craig Barrack

IPC: G01R31/08 ,  G06F11/00

CPC classification number: H04L12/462 ,  H04L43/10 ,  H04L45/02 ,  H04L45/22 ,  H04L45/28

Abstract: A hardware-based failover scheme enabling rapid end-to-end recovery is provided. Hardware logic periodically generates, transmits, receives, and processes heartbeat packets, sent from one end of the communications network to another, and then returned back. If a communications network node or communications link failure is being experienced along the transport path, then the hardware logic rapidly swaps the affected traffic conveyed to a pre-established backup transport path, typically within microseconds. Advantages are derived from the rapid failover effected end-to-end which enables continued delivery of provisioned communications services improving the resiliency and/or availability of a communications network.

Abstract translation: 提供了基于硬件的故障转移方案，实现快速的端到端恢复。 硬件逻辑周期性地生成，发送，接收和处理从通信网络的一端发送到另一端的心跳信息包，然后返回。 如果沿着传输路径遇到通信网络节点或通信链路故障，则硬件逻辑快速地将传送到预先建立的备份传输路径的受影响的业务交换，通常在微秒内。 优点来源于端对端的快速故障转移，从而能够持续提供所提供的通信服务，从而提高通信网络的弹性和/或可用性。

公开(公告)号：US07760719B2

公开(公告)日：2010-07-20

申请号：US10881226

申请日：2004-06-30

Applicant: James Yik ,  Rong-Feng Chang ,  Eric Lin ,  John Ta ,  Craig Barrack

Inventor： James Yik ,  Rong-Feng Chang ,  Eric Lin ,  John Ta ,  Craig Barrack

IPC: H04L12/28

CPC classification number: H04L49/3063 ,  H04L49/201 ,  H04L49/602

Abstract: A packet switching node in a pipelined architecture processing packets received via an input port associated with the packet switching node performs a method, which includes: determining a packet frame type; selectively extracting packet header field values specific to a packet frame type, including packet addressing information; ascribing to the packet a preliminary action to be performed; searching packet switching information tracked by the packet switching node based on extracted packet addressing information; formulating a preliminary switch response for the packet; classifying the packet into a packet flow; modifying the preliminary switch response in accordance with one of the preliminary action, the packet flow into which the packet was classified, and a default port action corresponding to the input port; modifying the packet header in accordance with one of the preliminary action, the packet flow, and the default port action; and processing the packet.

Abstract translation: 处理经由与分组交换节点相关联的输入端口接收的分组的流水线架构中的分组交换节点执行一种方法，其包括：确定分组帧类型; 选择性地提取特定于分组帧类型的分组报头字段值，包括分组寻址信息; 归因于要执行的初步动作; 基于提取的分组寻址信息来搜索由分组交换节点跟踪的分组交换信息; 制定分组的初步切换响应; 将分组分组成分组流; 根据预备动作，数据包被分类到的分组流中的一个以及与输入端口对应的默认端口动作来修改初始切换响应; 根据预备动作，分组流和默认端口动作之一修改分组报头; 并处理数据包。

公开(公告)号：US07415701B2

公开(公告)日：2008-08-19

申请号：US11060333

申请日：2005-02-17

Applicant: Yun Wang ,  Miaobo Chen ,  Eric Lin ,  Chris Elford ,  Suresh Srinivas

Inventor： Yun Wang ,  Miaobo Chen ,  Eric Lin ,  Chris Elford ,  Suresh Srinivas

IPC: G06F9/44 ,  G06F7/38

CPC classification number: G06F9/45516 ,  G06F9/445

Abstract: Methods and apparatus to support the execution of a managed application that is linked to a native library or application are disclosed. The disclosed methods and apparatus support a virtual machine that is associated with the same ISA as the executing platform, while the ISA of the native library or application is of a different ISA. The disclosed methods and apparatus also support the execution of a managed application that is linked with several native libraries or applications that are associated with several different ISAs respectively.

Abstract translation: 公开了支持与本地库或应用相关联的被管理应用的执行的方法和装置。 所公开的方法和装置支持与执行平台相同的ISA相关联的虚拟机，而本地库或应用的ISA是不同的ISA。 所公开的方法和装置还支持与分别与若干不同的ISA相关联的几个本地库或应用链接的被管理应用的执行。