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58 条记录 (耗时 0.037 秒)

    Instruction and logic for run-time evaluation of multiple prefetchers
    11.
    发明授权
    Instruction and logic for run-time evaluation of multiple prefetchers 有权
    多个预取器的运行时评估的指令和逻辑

    公开(公告)号：US09378021B2

    公开(公告)日：2016-06-28

    申请号：US14181032

    申请日：2014-02-14

    申请人： Zeshan A. Chishti ,  Christopher B. Wilkerson ,  Seth Pugsley ,  Peng-Fei Chuang ,  Robert L. Scott ,  Aamer Jaleel ,  Shih-Lien L. Lu ,  Kingsum Chow

    发明人： Zeshan A. Chishti ,  Christopher B. Wilkerson ,  Seth Pugsley ,  Peng-Fei Chuang ,  Robert L. Scott ,  Aamer Jaleel ,  Shih-Lien L. Lu ,  Kingsum Chow

    IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F9/00

    CPC分类号： G06F12/0862 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/383 ,  G06F2212/6026

    摘要： A processor includes a cache, a prefetcher module to select information according to a prefetcher algorithm, and a prefetcher algorithm selection module. The prefetcher algorithm selection module includes logic to select a candidate prefetcher algorithm determine and store memory addresses of predicted memory accesses of the candidate prefetcher algorithm when performed by the prefetcher module, determine cache lines accessed during memory operations, and evaluate whether the determined cache lines match the stored memory addresses. The prefetcher algorithm selection module further includes logic to adjust an accuracy ratio of the candidate prefetcher algorithm, compare the accuracy ratio with a threshold accuracy ratio, and determine whether to apply the first candidate prefetcher algorithm to the prefetcher module.

    摘要翻译： 处理器包括高速缓存，根据预取器算法选择信息的预取器模块以及预取器算法选择模块。 预取器算法选择模块包括选择候选预取器算法的逻辑，当由预取器模块执行时，确定并存储候选预取器算法的预测存储器访问的存储器地址，确定在存储器操作期间访问的高速缓存行，并且评估所确定的高速缓存行是否匹配 存储的存储器地址。 预取器算法选择模块还包括用于调整候选预取器算法的准确率的逻辑，将精度比与阈值精度比进行比较，并且确定是否将第一候选预取器算法应用于预取器模块。

    Number representation and memory system for arithmetic
    12.
    发明授权
    Number representation and memory system for arithmetic 有权
    数字表示和算术记忆系统

    公开(公告)号：US09223544B2

    公开(公告)日：2015-12-29

    申请号：US13606998

    申请日：2012-09-07

    申请人： Helia Naeimi ,  Ralph Nathan ,  Shih-Lien L. Lu ,  John L. Gustafson

    发明人： Helia Naeimi ,  Ralph Nathan ,  Shih-Lien L. Lu ,  John L. Gustafson

    IPC分类号： G06F7/483 ,  G06F7/38 ,  G06F7/499

    CPC分类号： G06F7/483 ,  G06F7/38 ,  G06F7/49989

    摘要： A method, device and system for representing numbers in a computer including storing a floating-point number M in a computer memory; representing the floating-point number M as an interval with lower and upper bounds A and B when it is accessed by using at least two floating-point numbers in the memory; and then representing M as an interval with lower and upper bounds A and B when it is used in a calculation by using at least three floating-point numbers in the memory. Calculations are performed using the interval and when the data is written back to the memory it may be stored as an interval if the size of the interval is significant, i.e. larger than a first threshold value. A warning regarding the suspect accuracy of any data stored as an interval may be issued if the interval is too large, i.e. larger than a second threshold value.

    摘要翻译： 一种用于在计算机中表示数字的方法，装置和系统，包括将浮点数M存储在计算机存储器中; 当通过使用存储器中的至少两个浮点数来访问时，将浮点数M表示为具有下限和上限A和B的间隔; 然后当在计算中使用存储器中的至少三个浮点数时，将M表示为具有下限和上限A和B的间隔。 使用间隔执行计算，并且当数据被写回存储器时，如果间隔的大小是显着的，即大于第一阈值，则可将其存储为间隔。 如果间隔太大，即大于第二阈值，则可以发出关于作为间隔存储的任何数据的可疑精度的警告。

    Memory cell without halo implant
    13.
    发明授权
    Memory cell without halo implant 有权
    无光晕植入的记忆细胞

    公开(公告)号：US07355246B2

    公开(公告)日：2008-04-08

    申请号：US11268430

    申请日：2005-11-07

    申请人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

    发明人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

    IPC分类号： H01L29/76

    CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/0207 ,  H01L27/0214 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108

    摘要： Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.

    摘要翻译： 一些实施例提供一种存储单元，其包括掺杂有第一类型的电荷载体的体区，设置在体区中的源极区，并掺杂有第二类型的电荷载流子，以及设置在体区中的掺杂电荷 第二种载体。 根据一些实施例，身体区域，源区域和漏极区域在第一方向上定向，身体区域和源区域形成第一结，并且体区域和漏区域形成第二结。 此外，在第一结无偏置的情况下，从体区到源极区的第一结的导电率基本上小于从体区到漏区的第二结的导电率，在第二结 是不偏不倚的 一些实施例还包括在第二方向上取向的晶体管，其中第二方向不平行于第一方向。

    Non-stalling circular counterflow pipeline processor with recorder buffer
    16.
    发明授权
    Non-stalling circular counterflow pipeline processor with recorder buffer 失效
    具有记录缓冲器的非停滞循环逆流管线处理器

    公开(公告)号：US06691222B2

    公开(公告)日：2004-02-10

    申请号：US10391241

    申请日：2003-03-18

    申请人： Kenneth J. Janik ,  Shih-Lien L. Lu ,  Michael F. Miller

    发明人： Kenneth J. Janik ,  Shih-Lien L. Lu ,  Michael F. Miller

    IPC分类号： G06F1500

    CPC分类号： G06F9/3865 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867

    摘要： A system and method of executing instructions within a counterflow pipeline processor. The counterflow pipeline processor includes an instruction pipeline, a data pipeline, a reorder buffer and a plurality of execution units. An instruction and one or more operands issue into the instruction pipeline and a determination is made at one of the execution units whether the instruction is ready for execution. If so, the operands are loaded into the execution unit and the instruction executes. The execution unit is monitored for a result and, when the result arrives, it is stored into the result pipeline. If the instruction reaches the end of the pipeline without executing it wraps around and is sent down the instruction pipeline again.

    摘要翻译： 在逆流管线处理器内执行指令的系统和方法。 逆流管线处理器包括指令流水线，数据流水线，重排序缓冲器和多个执行单元。 指令和一个或多个操作数发出到指令流水线中，并且在执行单元之一确定指令是否准备好执行。 如果是这样，操作数被加载到执行单元中，并执行指令。 监视执行单元的结果，当结果到达时，将其存储到结果流水线中。 如果指令到达流水线的末端，而不执行它，并重新发送指令管道。

    Register file scheme
    18.
    发明授权
    Register file scheme 有权

    公开(公告)号：US06608775B2

    公开(公告)日：2003-08-19

    申请号：US10067491

    申请日：2002-02-04

    申请人： Shih-Lien L. Lu ,  Konrad Lai

    发明人： Shih-Lien L. Lu ,  Konrad Lai

    IPC分类号： G11C1100

    CPC分类号： G11C8/16

    摘要： A circuit including a plurality of latches including feedback control circuitry and a plurality of data input terminals and data output terminals respectively coupled to alternative sides of said plurality of latches.

    Register file scheme
    20.
    发明授权
    Register file scheme 失效
    注册文件方案

    公开(公告)号：US06430083B1

    公开(公告)日：2002-08-06

    申请号：US09606577

    申请日：2000-06-28

    申请人： Shih-Lien L. Lu ,  Konrad Lai

    发明人： Shih-Lien L. Lu ,  Konrad Lai

    IPC分类号： G11C1100

    CPC分类号： G11C8/16

    摘要： A circuit including a plurality of latches including feedback control circuitry and a plurality of data input terminals and data output terminals respectively coupled to alternative sides of said plurality of latches.

    摘要翻译： 包括多个锁存器的电路包括反馈控制电路和分别耦合到所述多个锁存器的替代侧的多个数据输入端子和数据输出端子。