公开(公告)号：US10539846B2

公开(公告)日：2020-01-21

申请号：US16109834

申请日：2018-08-23

Applicant: Japan Display Inc.

Inventor： Yohei Yamaguchi ,  Arichika Ishida ,  Hidekazu Miyake ,  Hiroto Miyake ,  Isao Suzumura

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L27/12 ,  H01L29/786 ,  G02F1/1343 ,  H01L29/423

Abstract: According to one embodiment, a display device includes an insulating substrate, a thin-film transistor including a semiconductor layer formed on a layer above the insulating substrate, a gate electrode which at least partly overlaps the semiconductor layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer, and a light shielding layer formed between the thin-film transistor and the insulating substrate to at least partly overlap the semiconductor layer, the light shielding layer electrically connected to the gate electrode.

公开(公告)号：US09372376B2

公开(公告)日：2016-06-21

申请号：US14105496

申请日：2013-12-13

Applicant: Japan Display Inc. ,  Panasonic Liquid Crystal Display Co., Ltd.

Inventor： Terunori Saitou ,  Hidekazu Miyake ,  Takuo Kaitoh ,  Yoshiharu Owaku

IPC: G02F1/1345 ,  G02F1/1362 ,  G02F1/1333

CPC classification number: G02F1/13458 ,  G02F1/1333 ,  G02F1/136204 ,  G02F2001/133388 ,  G02F2202/103 ,  G02F2202/22

Abstract: A method of manufacturing a liquid crystal display device having a substrate with a display area, a control area adjacent to the display area, and terminals. The method includes forming an interlayer insulating film and an a-Si film below an image signal line in the display area and below a line in the same layer as the image signal line in the control area, forming a scribing line outside the terminals, forming a ground line in the same layer as the scan line outside the scribing line, forming the interlayer insulating film outside the terminal, without forming the a-Si film on the interlayer insulating film, forming a static electricity protection line coupled to the terminal on the interlayer insulating film, the static electricity protection line being coupled to other static electricity protection lines outside the ground line, and, after the steps above, separating the substrate along the scribing line.

Abstract translation: 一种液晶显示装置的制造方法，其具有具有显示区域的基板，与显示区域相邻的控制区域以及端子。 该方法包括在显示区域中的图像信号线下方形成层间绝缘膜和a-Si膜，并且在与控制区域中的图像信号线相同的层下面的线下方，在端子外部形成划线，形成 与划线之外的扫描线相同的层中的接地线，在端子外部形成层间绝缘膜，而不在层间绝缘膜上形成a-Si膜，形成在端子上连接的静电保护线 层间绝缘膜，静电保护线与地线外的其他静电保护线相连，并且在上述步骤之后，沿着划刻线分离衬底。

公开(公告)号：US20150055046A1

公开(公告)日：2015-02-26

申请号：US14533561

申请日：2014-11-05

Applicant: Japan Display Inc. ,  Panasonic Liquid Crystal Display Co., Ltd.

Inventor： Jun Fujiyoshi ,  Yasukazu Kimura ,  Hideo Tanabe ,  Masataka Okamoto ,  Hidekazu Miyake

IPC: G02F1/1333 ,  G02F1/1335 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: G02F1/133305 ,  G02F1/133345 ,  G02F1/133514 ,  G02F1/134363 ,  G02F1/136227 ,  G02F1/1368

Abstract: A liquid crystal display device includes a plurality of pixels, each including a thin-film transistor and a pixel electrode formed above a substrate, and an organic insulation film formed between one electrode of the thin-film transistor and the pixel electrode. The one electrode and the pixel electrode are connected through a contact hole formed in the organic insulation film, and a sidewall of the contact hole, which is made of the organic insulation film, is tapered. An underlying layer beneath the organic insulation film, in contact with to the organic insulation film, includes a lowermost plane extending substantially in parallel to a plane of the substrate and an uppermost plane extending substantially in parallel to the plane of the substrate. A single step of the underlying layer is formed so as to extend between the lowermost plane and the uppermost plane.

Abstract translation: 液晶显示装置包括多个像素，每个像素包括形成在基板上的薄膜晶体管和像素电极，以及形成在薄膜晶体管的一个电极和像素电极之间的有机绝缘膜。 一个电极和像素电极通过形成在有机绝缘膜中的接触孔连接，并且由有机绝缘膜制成的接触孔的侧壁是锥形的。 与有机绝缘膜接触的有机绝缘膜下面的下层包括基本上平行于衬底的平面延伸的最下面的平面和基本平行于衬底的平面延伸的最上面。 底层的单一步骤形成为在最下平面和最上平面之间延伸。

公开(公告)号：US12271088B2

公开(公告)日：2025-04-08

申请号：US18428228

申请日：2024-01-31

Applicant: Japan Display Inc.

Inventor： Yohei Yamaguchi ,  Arichika Ishida ,  Hidekazu Miyake ,  Hiroto Miyake ,  Isao Suzumura

IPC: G02F1/1368 ,  G02F1/1343 ,  G02F1/1362 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first metal layer on the insulating substrate, a first insulating layer on the insulating substrate and the first metal layer, a semiconductor layer on the first insulating layer, a second insulating layer on the semiconductor layer and the first insulating layer, a second metal layer on the second insulating layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer. The first metal layer overlaps the second metal layer. A third metal layer contacts a top surface of the second metal layer and a top surface of the first metal layer.

公开(公告)号：US12100709B2

公开(公告)日：2024-09-24

申请号：US18480552

申请日：2023-10-04

Applicant: Japan Display Inc.

Inventor： Isao Suzumura ,  Kazufumi Watabe ,  Yoshinori Ishii ,  Hidekazu Miyake ,  Yohei Yamaguchi

IPC: H01L27/12 ,  G02F1/133 ,  G02F1/1362 ,  G02F1/1368 ,  H01L29/24 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H10K59/121

CPC classification number: H01L27/1225 ,  G02F1/13306 ,  G02F1/136209 ,  G02F1/1368 ,  H01L27/1251 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/78633 ,  H01L29/78675 ,  H01L29/7869 ,  G02F1/13685 ,  G02F2202/10 ,  G02F2202/104 ,  H10K59/1213

Abstract: The object of the present invention is to make it possible to form an LTPS TFT and an oxide semiconductor TFT on the same substrate. A display device includes a substrate having a display region in which pixels are formed. The pixel includes a first TFT using an oxide semiconductor 109. An oxide film 110 as an insulating material is formed on the oxide semiconductor 109. A gate electrode 111 is formed on the oxide film 110. A first electrode 115 is connected to a drain of the first TFT via a first through hole formed in the oxide film 110. A second electrode 116 is connected to a source of the first TFT via a second through hole formed in the oxide film 110.

公开(公告)号：US11056514B2

公开(公告)日：2021-07-06

申请号：US15659796

申请日：2017-07-26

Applicant: Japan Display Inc.

Inventor： Yoshinori Ishii ,  Kazufumi Watabe ,  Hidekazu Miyake

IPC: H01L27/12 ,  G02F1/13 ,  G02F1/1333 ,  G02F1/1362 ,  G02F1/1368 ,  H01L27/32 ,  H01L51/52 ,  H01L51/56 ,  G02F1/1343

Abstract: Separation of wirings formed on an organic passivation film is prevented in an organic EL display device or a liquid crystal display device. The organic EL display device includes a TFT formed on a substrate and an organic passivation film formed to cover the TFT. An intermediate film containing SiO or SiN is formed to cover the organic passivation film. An insulation film formed with an organic material is formed on the intermediate film. A reflective electrode is formed on the intermediate film. The reflective electrode is connected to the TFT via a through-hole formed in the organic passivation film and a through-hole formed in the intermediate film.

公开(公告)号：US10403652B2

公开(公告)日：2019-09-03

申请号：US15661086

申请日：2017-07-27

Applicant: Japan Display Inc.

Inventor： Yoshinori Ishii ,  Kazufumi Watabe ,  Hidekazu Miyake

IPC: H01L27/12 ,  H01L33/00 ,  H01L29/786 ,  G02F1/13 ,  G02F1/1333 ,  G02F1/1368 ,  H01L27/32 ,  H01L51/52 ,  G02F1/1362

Abstract: An organic EL display device has a semiconductor circuit substrate comprising a TFT and an organic passivation layer thereon. An AlO layer is formed over the organic passivation layer, and an electrode layer is formed on the AlO layer. The electrode layer connects with TFT via a through hole formed in the AlO layer and in the organic passivation layer.

公开(公告)号：US09709853B2

公开(公告)日：2017-07-18

申请号：US14480804

申请日：2014-09-09

Applicant: Japan Display Inc.

Inventor： Norihiro Uemura ,  Hidekazu Miyake ,  Isao Suzumura ,  Yohei Yamaguchi ,  Toshiki Kaneko

IPC: G02F1/1345 ,  G02F1/1337 ,  G02F1/1362 ,  G02F1/1333

CPC classification number: G02F1/133788 ,  G02F1/136209 ,  G02F2001/133388

Abstract: To maintain good operation of a peripheral circuit using an oxide thin film transistor in a liquid crystal display panel to which photo alignment is applied, the liquid crystal display panel includes: a transparent substrate provided with an oxide thin film transistor in the periphery of a pixel portion in which pixel electrodes are arranged, to control the pixel electrodes; and an alignment film to align liquid crystal provided in the pixel portion. The alignment film is subjected to photo alignment treatment by ultraviolet irradiation. Further, an ultraviolet absorbing layer is provided so as to cover the oxide thin film transistor. For example, an alignment film is used for the ultraviolet absorbing layer to absorb the ultraviolet light for the photo aliment treatment of the alignment film, in the peripheral circuit portion for controlling the pixel electrodes, thereby preventing the threshold voltage of the oxide thin film transistor from shifting.

公开(公告)号：US09660039B2

公开(公告)日：2017-05-23

申请号：US15062887

申请日：2016-03-07

Applicant: Japan Display Inc.

Inventor： Hidekazu Miyake ,  Arichika Ishida ,  Hiroto Miyake ,  Isao Suzumura ,  Yohei Yamaguchi

IPC: H01L29/49 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/78696

Abstract: According to one embodiment, a thin-film transistor includes a semiconductor layer SC including a channel region, and a source region and a drain region on both sides of the channel region, a gate electrode GE, a first electrode SE connected to the source region via a first contact hole CH1, a second electrode DE connected to the drain region via a second contact hole CH2, a source line connected to the first electrode, and a drain line connected to the second electrode. A distance from the first and second contact holes to an end of the respective regions in a direction of a channel width is greater than or equal to 5 μm and less than or equal to 30 μm. The source line and the drain line extend in directions different from each other.

公开(公告)号：US09620526B2

公开(公告)日：2017-04-11

申请号：US15015445

申请日：2016-02-04

Applicant: Japan Display Inc.

Inventor： Isao Suzumura ,  Norihiro Uemura ,  Hidekazu Miyake ,  Yohei Yamaguchi

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L21/473 ,  H01L21/02 ,  H01L21/3213

CPC classification number: H01L27/1225 ,  H01L21/02071 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/32138 ,  H01L21/32139 ,  H01L21/473 ,  H01L27/1248 ,  H01L27/127 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

Abstract: There is provided a bottom gate channel etched thin film transistor that can suppress initial Vth depletion and a Vth shift. A thin film transistor is formed, including a gate electrode interconnection disposed on a substrate, a gate insulating film, an oxide semiconductor layer to be a channel layer, a stacked film of a source electrode interconnection and a first hard mask layer, a stacked film of a drain electrode interconnection and a second hard mask layer, and a protective insulating film.