公开(公告)号：US06034895A

公开(公告)日：2000-03-07

申请号：US198431

申请日：1998-11-24

Applicant: David Naura ,  Jean Devin

Inventor： David Naura ,  Jean Devin

IPC: G11C16/12 ,  G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/12

Abstract: A method and apparatus for the programming and erasure of a memory cell made out of floating-gate transistors and to the circuit pertaining thereto is described. It can be applied especially to non-volatile electrically erasable and programmable memories, for example EEPROMs and flash EPROMs. A programming voltage or erasure voltage comprising a voltage shift equal in value to a reference voltage is produced, followed by a voltage ramp comprising a rising phase followed possibly by voltage plateau, this voltage ramp being shifted in voltage by the value of the reference voltage and being followed, in turn, by a voltage drop. The value of the voltage shift is fixed at an intermediate value that is lower than the value of a so-called tunnel voltage of the memory cell but greater than the supply voltage.

Abstract translation: 描述了由浮栅晶体管制成的存储单元的编程和擦除以及与其有关的电路的方法和装置。 它可以特别适用于非易失性电可擦除和可编程存储器，例如EEPROM和闪存EPROM。 产生包括与参考电压值相等的电压偏移的编程电压或擦除电压，随后是包括可能伴随电压平台的上升相的电压斜坡，该电压斜坡在电压上移动参考电压的值， 随之而来的是电压降。 电压偏移的值固定在比存储单元的所谓的隧道电压的值低的值的中间值，但大于电源电压。

公开(公告)号：US5991199A

公开(公告)日：1999-11-23

申请号：US12938

申请日：1998-01-22

Applicant: Alessandro Brigati ,  Jean Devin ,  Bruno Leconte

Inventor： Alessandro Brigati ,  Jean Devin ,  Bruno Leconte

IPC: G11C16/02 ,  G11C16/10 ,  G11C16/12 ,  G11C11/00

CPC classification number: G11C16/12 ,  G11C16/10

Abstract: In a device for programming EPROM-Flash type memory cells of memory words of a memory, a bit line of a memory cell of a given rank of the first word and at least one bit line of a memory cell of the same rank in a word that is horizontally adjacent to this first word are connected together to two common programming connections by means of a bias circuit, and the bias circuit comprises two bias voltage inputs and one bias voltage output. The programming method consists in the successive programming, during different programming cycles, of the different cells of this first word and, during the same programming cycle, a different cell, of the same rank, in at least one word that is different from this first word is programmed.

Abstract translation: 在用于对存储器的存储器字的EPROM-Flash型存储单元进行编程的装置中，第一字的给定秩的存储器单元的位线和字中相同等级的存储器单元的至少一个位线 水平相邻的第一个字通过偏置电路连接到两个公共编程连接，偏置电路包括两个偏置电压输入和一个偏置电压输出。 该编程方法包括在不同的编程周期期间在该第一个字的不同单元中的连续编程，并且在相同的编程周期期间，在至少一个不同于该第一个单词的单词中具有同一等级的不同单元 字被编程。

公开(公告)号：US5537349A

公开(公告)日：1996-07-16

申请号：US361996

申请日：1994-12-21

Applicant: Jean Devin

Inventor： Jean Devin

IPC: G11C17/00 ,  G11C7/12 ,  G11C16/06 ,  G11C16/24 ,  G11C16/26 ,  G11C16/04

CPC classification number: G11C7/12 ,  G11C16/24 ,  G11C16/26

Abstract: A random-access memory with an accelerated access time. One or more of the preliminary operations of the sequence of operations carried out for accessing the memory are anticipated by performing the anticipated operation or operations during the end of a sequence of a previous memory access. The anticipated operation is preferably that of the deselection of the bit lines of the memory.

Abstract translation: 具有加速访问时间的随机存取存储器。 通过在先前的存储器访问的序列的结束期间执行预期的操作或操作来预期用于访问存储器的操作序列的一个或多个初步操作。 预期的操作优选地是取消选择存储器的位线。

公开(公告)号：US5058069A

公开(公告)日：1991-10-15

申请号：US466620

申请日：1990-01-17

Applicant: Jean Marie Gaultier ,  Jean Devin

Inventor： Jean Marie Gaultier ,  Jean Devin

IPC: G11C29/00

CPC classification number: G11C29/785 ,  G11C29/808

Abstract: A device for the addressing of redundant elements of an integrated circuit memory is disclosed. This memory comprises an array of row memory elements and column memory elements, respectively addressable by row addresses and column addresses, and at least one group of fuses to store the address of a faulty element of the memory. Each fuse is associated with a row/column address pair. Through the blowing of certain fuses in the group after testing of a memory element, the address either of a column element, if the faulty element is a column element, or of a row element, if the faulty element is a row element, is stored. Only the row addresses are enabled when the stored address is that of a row element, and only the column addresses are enabled when the stored address is that of a column element, in order to address either a row redundant element or a column redundant element.

Abstract translation: 公开了一种用于寻址集成电路存储器的冗余元件的装置。 该存储器包括分别可由行地址和列地址寻址的行存储器元件和列存储器元件的阵列，以及存储存储器的故障元件的地址的至少一组保险丝。 每个保险丝与行/列地址对相关联。 通过在测试存储器元件之后吹送组中的某些熔丝，存储列元素的地址，如果有缺陷的元素是列元素或行元素，则如果有故障元素是行元素，则存储 。 当存储的地址是行元素的地址时，只有行地址被使能，而当存储的地址是列元素的存储地址时，只有列地址被启用，以便寻址行冗余元素或列冗余元素。

公开(公告)号：US20110202948A1

公开(公告)日：2011-08-18

申请号：US13027834

申请日：2011-02-15

Applicant: Marco Bildgen ,  Jean Devin

Inventor： Marco Bildgen ,  Jean Devin

IPC: H04H60/32 ,  G06F21/02 ,  G06F21/22 ,  G06F19/00

CPC classification number: H04N7/1675 ,  G06F21/10 ,  G06F21/552 ,  G06F21/77 ,  G06F2221/0797 ,  G06F2221/2105 ,  G06F2221/2151 ,  G06F2221/2153 ,  H04L9/004 ,  H04L9/0637 ,  H04L63/1441 ,  H04N21/4181 ,  H04N21/4424 ,  H04N21/4432 ,  H04N21/4623

Abstract: A method may be for detecting potentially suspicious operation of an electronic device configured to operate in the course of activity sessions. The method may include within the device, a metering, from an initial instant of the number of activity sessions having a duration below a first threshold, and a comparison of this number with a second threshold.

Abstract translation: 一种方法可以用于检测被配置为在活动会话过程中操作的电子设备的潜在的可疑操作。 所述方法可以在所述设备内包括从具有低于第一阈值的持续时间的活动会话的数量的初始时刻的计量，以及所述数量与第二阈值的比较。

公开(公告)号：US07453732B2

公开(公告)日：2008-11-18

申请号：US11742334

申请日：2007-04-30

Applicant: Jean Devin

Inventor： Jean Devin

IPC: G11C11/34

CPC classification number: G11C16/3454 ,  G11C16/10

Abstract: The present invention relates to a method for programming a memory cell having a determined transconductance curve. The programming of the memory cell comprises a series of programming cycles each comprising a step of verifying the state of the memory cell. According to the present invention, the verify step comprises a first read of the memory cell with a first read voltage greater than a reference threshold voltage, and a second read of the memory cell with a second read voltage lower than or equal to the reference threshold voltage. The memory cell is considered not to be in the programmed state if first- and second-read currents flowing through the memory cell are above determined thresholds, and programming voltage pulses are applied to the memory cell while the latter is not in the programmed state. Application in particular to the programming of Flash memory cells.

Abstract translation: 本发明涉及一种用于对具有确定的跨导曲线的存储单元进行编程的方法。 存储器单元的编程包括一系列编程周期，每个编程周期包括验证存储器单元的状态的步骤。 根据本发明，验证步骤包括具有大于参考阈值电压的第一读取电压的存储器单元的第一次读取，以及具有低于或等于参考阈值的第二读取电压的存储器单元的第二次读取 电压。 如果流过存储单元的第一和第二读取电流高于确定的阈值，则存储单元被认为不处于编程状态，并且编程电压脉冲被施加到存储单元而后者不处于编程状态。 特别适用于闪存单元的编程。

公开(公告)号：US06807103B2

公开(公告)日：2004-10-19

申请号：US10438733

申请日：2003-05-15

Applicant: Paola Cavaleri ,  Bruno Leconte ,  Sébastien Zink ,  Jean Devin

Inventor： Paola Cavaleri ,  Bruno Leconte ,  Sébastien Zink ,  Jean Devin

IPC: G11C700

CPC classification number: G11C16/3431 ,  G11C16/16 ,  G11C16/3418

Abstract: The present invention relates to a page-erasable FLASH memory including a memory array having a plurality of pages each with floating-gate transistors connected by their gates to word lines, a word line decoder connected to the word lines of the memory, and the application of a positive erase voltage to the source or drain electrodes of all the floating-gate transistors of a sector forming a page to be erased. According to the present invention, the word line decoder includes a unit for applying, when a page is being erased, a negative erase voltage to the gates of the transistors of the page to be erased, while applying a positive inhibit voltage to the gates of the transistors of at least one page that is not to be erased.

Abstract translation: 本发明涉及一种可擦除闪存存储器，其包括具有多个页面的存储器阵列，每个页面各自具有通过其栅极连接到字线的浮栅晶体管，连接到存储器的字线的字线解码器和应用 的正擦除电压施加到形成要擦除的页的扇区的所有浮栅晶体管的源电极或漏电极。 根据本发明，字线解码器包括一个单元，用于当正被擦除页面时，向待擦除的页面的晶体管的栅极施加负的擦除电压，同时向第 至少一个页面的晶体管不被擦除。

公开(公告)号：US06219277B1

公开(公告)日：2001-04-17

申请号：US09300527

申请日：1999-04-27

Applicant: Jean Devin ,  David Naura ,  Sebastien Zink

Inventor： Jean Devin ,  David Naura ,  Sebastien Zink

IPC: G11C700

CPC classification number: G11C16/28

Abstract: A device and method for the reading of cells of an EEPROM is provided. The device includes at least one reference cell and one circuit for comparison between a current flowing into the reference cell and a current flowing in a cell selected in read mode. The reference cell is in a programmed state. The programming of the reference cell is done after the control reading and during the integrated circuit power-on reset phase, activated by the powering on of the integrated circuit.

Abstract translation: 提供了一种用于读取EEPROM单元的装置和方法。 该装置包括至少一个参考单元和一个电路，用于比较流入参考单元的电流和在读取模式中选择的单元中流动的电流。 参考单元处于编程状态。 参考单元的编程在控制读取之后和在集成电路上电复位阶段期间完成，由集成电路的供电激活。

公开(公告)号：US5959886A

公开(公告)日：1999-09-28

申请号：US9088

申请日：1998-01-20

Applicant: Jean Devin ,  Alessandro Brigati ,  Bruno Leconte

Inventor： Jean Devin ,  Alessandro Brigati ,  Bruno Leconte

IPC: G11C16/10 ,  G11C16/32 ,  G11C16/04

CPC classification number: G11C16/32 ,  G11C16/10

Abstract: A circuit for activating page-write operations in a floating-gate memory includes a first and a second time lag circuit. A resetting signal resets a first time lag whenever a word is written in a buffer of the memory. The first time lag circuit provides a state bit indicating that the first time lag has ended or not ended. The second time lag circuit activates a second time lag at the end of the first time lag and the end of the second time lag activates the writing of the page in the memory. The invention also relates to a method of writing in memory that uses a first and a second time lag.

Abstract translation: 用于在浮动栅存储器中激活页写操作的电路包括第一和第二时滞电路。 每当将字写入存储器的缓冲器中时，复位信号复位第一次滞后。 第一时滞电路提供指示第一时滞已经结束或未结束的状态位。 第二时间滞后电路在第一时间延迟结束时激活第二时间滞后，并且第二时间延迟的结束激活了在存储器中写入页面。 本发明还涉及一种在存储器中写入使用第一和第二时滞的方法。

公开(公告)号：US5950224A

公开(公告)日：1999-09-07

申请号：US797948

申请日：1997-02-12

Applicant: Jean Devin

Inventor： Jean Devin

IPC: G11C11/56 ,  G06F12/16

CPC classification number: G11C16/3418 ,  G11C11/56 ,  G11C11/5621 ,  G11C16/3431

Abstract: An electrically modifiable multilevel non-volatile memory has autonomous refresh means. The multilevel memory has a real-time clock delivering pulses to periodically activate an operation for refreshing the memory cells of the main matrix. The memory has application to the field of large-capacity memories, for example, several tens of megabits and more.

Abstract translation: 电可修改的多级非易失性存储器具有自主刷新装置。 多电平存储器具有传送脉冲的实时时钟以周期性地激活用于刷新主矩阵的存储器单元的操作。 该内存已经应用于大容量存储器领域，例如几十兆位以上。