公开(公告)号：US06822909B1

公开(公告)日：2004-11-23

申请号：US10422090

申请日：2003-04-24

申请人： Darlene G. Hamilton ,  Edward Hsia ,  Mark W. Randolph ,  Edward F. Runnion ,  Kulachet Tanpairoj

发明人： Darlene G. Hamilton ,  Edward Hsia ,  Mark W. Randolph ,  Edward F. Runnion ,  Kulachet Tanpairoj

IPC分类号： G11C1134

CPC分类号： G11C16/0475 ,  G11C11/5671 ,  G11C16/3454

摘要： A method of programming a dual cell memory device having a first charge storing cell and a second charge storing cell. The method can include applying an initial program pulse to the memory device; comparing the threshold voltage of the memory device with a verify threshold voltage; and if the threshold voltage of the memory device is less than the verify threshold voltage, applying a second program pulse to the memory device during which at least one condition of the second program pulse is modified from the initial program pulse.

摘要翻译： 一种编程具有第一电荷存储单元和第二电荷存储单元的双单元存储器件的方法。 该方法可以包括将初始编程脉冲施加到存储器件; 将存储器件的阈值电压与验证阈值电压进行比较; 并且如果所述存储器件的阈值电压小于所述验证​​阈值电压，则向所述存储器件施加第二编程脉冲，在所述存储器件期间，从所述初始编程脉冲修改所述第二编程脉冲的至少一个条件。

公开(公告)号：US5870407A

公开(公告)日：1999-02-09

申请号：US653211

申请日：1996-05-24

申请人： Edward Hsia ,  Jose H. Hernandez ,  Sayan Suanya

发明人： Edward Hsia ,  Jose H. Hernandez ,  Sayan Suanya

IPC分类号： G11C29/00 ,  G11C29/50

CPC分类号： G11C29/006 ,  G11C29/50 ,  G11C16/04

摘要： In a semiconductor manufacturing process for manufacturing memory devices a method of screening hot temperature programmability rejects in memory devices during wafer sort at room temperature that would be rejected at class test at high temperature. All cells in the memory device are subjected to a first sequence of programming pulses at a voltage lower than the standard programming voltage. The number of pulses in the first sequence of programming pulses is from 1-5. Those die that verify as having been successfully programmed are passed. Those die that do not verify as having been programmed are subjected to a second sequence of programming pulses at a voltage lower than the standard programming voltage. The number of pulses in the second sequence of programming pulses is from 10 to 15 pulses. Those that verify as being programmed are marked as good and those that do not are repaired and retested.

摘要翻译： 在用于制造存储器件的半导体制造工艺中，在室温下的晶片分选期间，在高温下的类别测试中被拒绝的情况下，在存储器件中筛选热温度可编程性的方法被拒绝。 存储器件中的所有单元以低于标准编程电压的电压经受第一编程脉冲序列。 编程脉冲的第一个序列中的脉冲数为1-5。 被验证为已经成功编程的那些死亡通过。 那些不能被验证为已编程的芯片在低于标准编程电压的电压下经受第二编程脉冲序列。 第二编程脉冲序列中的脉冲数为10至15个脉冲。 验证为编程的那些标记为好，那些没有被修复和重新测试。

公开(公告)号：US5751633A

公开(公告)日：1998-05-12

申请号：US655357

申请日：1996-05-24

申请人： Edward Hsia ,  Jose H. Hernandez ,  Sayan Suanya

发明人： Edward Hsia ,  Jose H. Hernandez ,  Sayan Suanya

IPC分类号： G11C29/52 ,  G11C11/34

CPC分类号： G11C29/52

摘要： In a semiconductor manufacturing process for manufacturing memory devices a method of screening hot temperature erase rejects in memory devices during wafer sort at room temperature that would be rejected at class test at high temperature. Selected cells of the memory device are subjected to a first sequence of erasure pulses at a high voltage until the selected cells are verified erased or until a first maximum number of erasure pulses has been reached, recording the number of pulses required to erase the selected cells, reading and repairing any defective memory cells, and subjecting all cells to a second sequence of erasure pulses until all cells are verified erased or until a maximum number of pulses has been reached wherein the second maximum number is a multiple of the recorded number.

摘要翻译： 在用于制造存储器件的半导体制造工艺中，在室温下进行晶片分选时，将在高温阶段测试中被拒绝的方法来筛选存储器件中的热温度擦除废弃物的方法。 存储器件的所选单元以高电压经受第一次擦除脉冲序列，直到所选择的单元被清除或直到达到第一最大数量的擦除脉冲为止，记录擦除所选单元所需的脉冲数 读取和修复任何有缺陷的存储器单元，以及对所有单元进行第二次擦除脉冲序列，直到所有单元被确认被擦除或直到达到最大数量的脉冲为止，其中第二个最大数量是所记录数量的倍数。

公开(公告)号：US20120128612A1

公开(公告)日：2012-05-24

申请号：US13322667

申请日：2010-05-27

申请人： Jon Lenn ,  Hans Hofland ,  Edward Hsia

发明人： Jon Lenn ,  Hans Hofland ,  Edward Hsia

IPC分类号： A61K31/517 ,  A61K31/59 ,  A61P31/10 ,  A61K31/56

CPC分类号： A61K31/517 ,  A61K9/0014 ,  A61K9/7015 ,  A61K45/06 ,  A61K2300/00

摘要： The present invention relates generally to antifugal compositions. In an embodiment, the antifungal compositions are effective for application to nails and surrounding skin, and comprise at least one volatile solvent, at least one film forming substance, and at least one pyrimidone derivative of formula I, such as albaconazole. These compositions are capable of treating an infection caused by fungi, such as onychomychosis.

摘要翻译： 本发明一般涉及防水组合物。 在一个实施方案中，抗真菌组合物对于施用于指甲和周围皮肤是有效的，并且包含至少一种挥发性溶剂，至少一种成膜物质和至少一种式I的嘧啶酮衍生物，例如阿拉科唑。 这些组合物能够治疗由真菌引起的感染，例如甲真菌病。

公开(公告)号：US20110305646A1

公开(公告)日：2011-12-15

申请号：US13202780

申请日：2010-03-19

申请人： Jon Lenn ,  Hans Hofland ,  Barry Hunt ,  Edward Hsia

发明人： Jon Lenn ,  Hans Hofland ,  Barry Hunt ,  Edward Hsia

IPC分类号： A61K9/12 ,  A61P31/10 ,  A61K31/23

CPC分类号： A61K31/22 ,  A61K9/0014 ,  A61K9/12 ,  A61K9/7015 ,  A61K31/517 ,  A61K2300/00

摘要： The present invention relates to a method of treating a fungal condition caused by T. rubrum, by administering a composition comprising a fatty acid monoester of glycerol. According to an embodiment, the fatty acid monoester of glycerol is 1-monocaprin. According to another embodiment, the fungal condition is onychomycosis.

摘要翻译： 本发明涉及通过施用包含甘油的脂肪酸单酯的组合物来治疗由红霉素引起的真菌病症的方法。 根据一个实施方案，甘油的脂肪酸单酯是1-单甲孕酮。 根据另一个实施方案，真菌病症是甲真菌病。

公开(公告)号：US06791880B1

公开(公告)日：2004-09-14

申请号：US10431320

申请日：2003-05-06

申请人： Kazuhiro Kurihara ,  Binh Quang Le ,  Pau-Ling Chen ,  Darlene Hamilton ,  Edward Hsia

发明人： Kazuhiro Kurihara ,  Binh Quang Le ,  Pau-Ling Chen ,  Darlene Hamilton ,  Edward Hsia

IPC分类号： G11C1606

CPC分类号： G11C29/026 ,  G11C16/04 ,  G11C16/349 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5006

摘要： A non-volatile memory read circuit having adjustable current sources to provide end of life simulation. A flash memory device comprising a reference current source used to provide a reference current for comparison to the current of a memory cell being read, includes an adjustable current source in parallel with the memory cell being read, and an adjustable current source in parallel with the reference current source. The current from the memory cell, reference current source, and their parallel adjustable current sources are input to cascode circuits for conversion to voltages that are compared by a sense amplifier. The behavior of the cascode circuits and sense amplifier in response to changes in the memory cell and reference current source may be evaluated by adjusting the adjustable current sources so that the combined current at each input to the sense amplifier simulates the current of the circuit after aging or cycling.

摘要翻译： 具有可调节电流源以提供寿命终止模拟的非易失性存储器读取电路。 包括用于提供用于与正在读取的存储器单元的电流进行比较的参考电流的参考电流源的闪速存储器件包括与被读取的存储器单元并联的可调电流源，以及与可读电流源并联的可调电流源 参考电流源。 来自存储单元，参考电流源及其并联可调电流源的电流被输入到共源共栅电路，用于转换成由读出放大器比较的电压。 可以通过调节可调电流源来评估级联电路和读出放大器响应于存储器单元和参考电流源的变化的行为，使得在读出放大器的每个输入处的组合电流在老化之后模拟电路的电流 或骑自行车。

公开(公告)号：US06381550B1

公开(公告)日：2002-04-30

申请号：US09322195

申请日：1999-05-28

申请人： Edward Hsia ,  Phuong K. Banh ,  Darlene Hamilton

发明人： Edward Hsia ,  Phuong K. Banh ,  Darlene Hamilton

IPC分类号： G01N3700

CPC分类号： G11C16/3409 ,  G11C16/04 ,  G11C16/344 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012

摘要： A method of utilizing Fast Chip Erase to screen endurance rejects. Multiple sectors in a device are selected and a time necessary to program all cells in the sectors is monitored and if the monitored time exceeds a first time, the device fails. A time necessary to erase all the cells without any overerased cells is monitored and if the time exceeds a second time, the device fails. A time necessary to correct overerased cells is monitored and if the time exceeds a third time, the device fails. The total time from erase until overerase correction is achieved is monitored and if the total time exceeds a fourth time, the device fails. The total time to determine erasability is monitored and if this time exceeds a fifth time, the device fails.

摘要翻译： 利用快速芯片擦除来筛选耐力拒绝的方法。 选择设备中的多个扇区，并监视对扇区中的所有单元进行编程所需的时间，如果监视时间超过第一次，则设备将失败。 监视擦除所有没有任何过载单元的所有单元所需的时间，如果时间超过第二次，则设备将失败。 监视修正过度细胞的时间，如果时间超过第三次，则设备将失败。 监视从擦除到过高修正的总时间，如果总时间超过第四次，则设备发生故障。 监视确定可擦除性的总时间，如果此时间超过第五次，则设备将失败。

公开(公告)号：US06901010B1

公开(公告)日：2005-05-31

申请号：US10119366

申请日：2002-04-08

申请人： Darlene G. Hamilton ,  Eric M. Ajimine ,  Binh Le ,  Edward Hsia ,  Ken Tanpairoj

发明人： Darlene G. Hamilton ,  Eric M. Ajimine ,  Binh Le ,  Edward Hsia ,  Ken Tanpairoj

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C7/00

CPC分类号： G11C16/107 ,  G11C16/0475 ,  G11C16/3409 ,  G11C16/3445 ,  G11C2216/18

摘要： An erase methodology of flash memory cells in a multi-bit memory array with bits disposed in normal and complimentary locations. An erase verify of bits in the normal locations is performed and if a bit in the normal location fails and if the maximum erase pulse count has not been reached, erase pulses are applied to both the normal bit and the complimentary bit. An erase verify of bits in the complimentary locations is performed and if a bit in the complimentary location fails and if the maximum erase pulse count has not been reached, erase pulses are applied to both the complimentary and the normal bit locations. If the bits pass the erase verify, the bits are subjected to a soft programming verify. If the bits are overerased and if the soft programming pulse count has not been reached a soft programming pulse is applied to the overerased bit.

摘要翻译： 位于正常和互补位置的位的多位存储器阵列中的闪存单元的擦除方法。 执行正常位置中的位的擦除验证，并且如果正常位置中的位失败，并且如果还没有达到最大擦除脉冲计数，则将擦除脉冲施加到正常位和补充位。 执行补充位置中的位的擦除验证，并且如果补充位中的位失败，并且如果还没有达到最大擦除脉冲计数，则擦除脉冲将被施加到互补位和正常位位置。 如果这些位通过擦除验证，则这些位经过软编程验证。 如果这些位过高，并且如果没有达到软编程脉冲计数，则软编程脉冲将被施加到过高位。

公开(公告)号：US06778442B1

公开(公告)日：2004-08-17

申请号：US10422092

申请日：2003-04-24

申请人： Darlene G. Hamilton ,  Edward Hsia ,  Kulachet Tanpairoj ,  Alykhan Madhani ,  Mimi Lee

发明人： Darlene G. Hamilton ,  Edward Hsia ,  Kulachet Tanpairoj ,  Alykhan Madhani ,  Mimi Lee

IPC分类号： G11C1134

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3454

摘要： A method of programming a dual cell memory device having a first charge storing cell and a second charge storing cell. According to one aspect of the method, the method can include over-erasing the first and second charge storing cells to shift an erase state threshold voltage of the memory device to be lower than a natural state threshold voltage. According to another aspect of the method, the method can include programming the first and second charge storing cells to the same data state and verifying that the second programmed charge storing cell stores charge corresponding to the data state. If the verification fails, both charge storing cells can be re-pulsed.

摘要翻译： 一种编程具有第一电荷存储单元和第二电荷存储单元的双单元存储器件的方法。 根据该方法的一个方面，该方法可以包括过度擦除第一和第二电荷存储单元，以使存储器件的擦除状态阈值电压低于自然状态阈值电压。 根据该方法的另一方面，该方法可以包括将第一和第二电荷存储单元编程为相同的数据状态，并验证第二编程电荷存储单元存储对应于数据状态的电荷。 如果验证失败，则电荷存储单元可以被重新脉冲。

公开(公告)号：US5724365A

公开(公告)日：1998-03-03

申请号：US653227

申请日：1996-05-24

申请人： Edward Hsia ,  Darlene Hamilton ,  Jose H. Hernandez

发明人： Edward Hsia ,  Darlene Hamilton ,  Jose H. Hernandez

IPC分类号： G11C29/10 ,  G11C29/24 ,  G01R31/28

CPC分类号： G11C29/10 ,  G11C29/24

摘要： A method of testing Flash memory devices by performing wafer sort testing on main array cells and redundancy array cells of the Flash memory device and performing class testing on redundancy array cells only. There is a major savings of testing time with no decrease in quality of the final product.

摘要翻译： 通过在闪存设备的主阵列单元和冗余阵列单元上执行晶片排序测试，并仅在冗余阵列单元上执行类测试来测试闪存设备的方法。 测试时间节省了大量成本，而最终产品的质量却没有降低。