公开(公告)号：US06686757B1

公开(公告)日：2004-02-03

申请号：US09409217

申请日：1999-09-30

申请人： Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis ,  Jeffrey D. Birdsley ,  Michael R. Bruce

发明人： Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis ,  Jeffrey D. Birdsley ,  Michael R. Bruce

IPC分类号： G01R3128

CPC分类号： G01R31/311

摘要： According to an example embodiment of the present invention, a defect detection approach involves detecting the existence of defects in an integrated circuit as a function of at least one applied energy source. In response to energy that is applied to the integrated circuit, response signals are detected. A parameter including information such as amplitude, frequency, phase, or a spectrum is developed for a reference integrated circuit device and then compared to the detected response signal. The deviation in the response and reference signals, and the type of energy source used, are correlated to a particular defect in the device.

摘要翻译： 根据本发明的示例性实施例，缺陷检测方法包括检测作为至少一个应用能量源的函数的集成电路中的缺陷的存在。 响应于施加到集成电路的能量，检测响应信号。 为参考集成电路器件开发包括振幅，频率，相位或频谱等信息的参数，然后与检测到的响应信号进行比较。 响应和参考信号的偏差以及所使用的能量源的类型与设备中的特定缺陷相关。

公开(公告)号：US06483327B1

公开(公告)日：2002-11-19

申请号：US09409088

申请日：1999-09-30

申请人： Michael R. Bruce ,  Victoria J. Bruce ,  Jeffrey D. Birdsley ,  Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis

发明人： Michael R. Bruce ,  Victoria J. Bruce ,  Jeffrey D. Birdsley ,  Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis

IPC分类号： G01R31302

CPC分类号： G01R1/071 ,  G01R31/311

摘要： A method and system providing spatial and timing resolution for photoemission microscopy of an integrated circuit. A microscope having an objective lens forming a focal plane is arranged to view the integrated circuit, and an aperture element having an aperture is optically aligned in the back focal plane of the microscope. The aperture element is positioned for viewing a selected area of the integrated circuit. A position-sensitive avalanche photo-diode is optically aligned with the aperture to detect photoemissions when test signals are applied to the integrated circuit.

摘要翻译： 一种为集成电路的光电显微镜提供空间和时序分辨率的方法和系统。 具有形成焦平面的物镜的显微镜被布置成观看集成电路，并且具有孔的孔径元件在显微镜的后焦平面中被光学对准。 光圈元件被定位成用于观看集成电路的选定区域。 位置敏感的雪崩光电二极管与孔径光学对准以在测试信号被施加到集成电路时检测光电发射。

公开(公告)号：US06430728B1

公开(公告)日：2002-08-06

申请号：US09410147

申请日：1999-09-30

申请人： Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring

发明人： Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring

IPC分类号： G06F1750

CPC分类号： G01R31/307 ,  G10K15/046

摘要： According to an example embodiment, the present invention is directed to a system and method for analyzing an integrated circuit. A laser is directed to the back side of an integrated circuit and causes local heating, which generates acoustic energy in the circuit. The acoustic energy propagation in the integrated circuit is detected via at least two detectors. Using the detected acoustic energy from the detectors, at least one circuit defect is detected and located.

摘要翻译： 根据示例性实施例，本发明涉及用于分析集成电路的系统和方法。 激光被引导到集成电路的背面，并引起局部加热，其在电路中产生声能。 通过至少两个检测器检测集成电路中的声能传播。 使用来自检测器的检测到的声能，检测和定位至少一个电路缺陷。

公开(公告)号：US06414335B1

公开(公告)日：2002-07-02

申请号：US09864688

申请日：2001-05-23

申请人： Rama R. Goruganthu ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone ,  Jeffrey D. Birdsley

发明人： Rama R. Goruganthu ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone ,  Jeffrey D. Birdsley

IPC分类号： H01L2358

CPC分类号： G01R31/312 ,  G01R31/307

摘要： Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by capacitively coupling a signal to the die. According to an example embodiment of the present invention, a die having a thinned back side is analyzed by capacitively coupling an input signal through the insulator portion of the SOI structure and effecting a state change to circuitry in the die. The state change is used to evaluate a characteristic of the die, such as by detecting a response to the state change. The ability to force such a state change is helpful for evaluating dies having SOI structure, and is particularly useful for evaluation techniques that require or benefit from maintaining the insulator portion of the SOI structure intact.

摘要翻译： 通过将信号电容耦合到管芯来增强具有绝缘体上硅（SOI）结构的半导体管芯的分析。 根据本发明的示例性实施例，通过电容耦合通过SOI结构的绝缘体部分的输入信号并对模具中的电路进行状态分析来分析具有减薄背侧的管芯。 状态变化用于评估管芯的特性，例如通过检测对状态变化的响应。 强制这种状态变化的能力有助于评估具有SOI结构的管芯，并且对于需要或受益于保持SOI结构的绝缘体部分而完整的评估技术特别有用。

公开(公告)号：US06576484B1

公开(公告)日：2003-06-10

申请号：US09864668

申请日：2001-05-23

申请人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone

发明人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone

IPC分类号： H01L2100

CPC分类号： H01L23/3735 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor analysis is enhanced using a system and method for improving the heat-dissipation characteristics of a semiconductor die. According to an example embodiment of the present invention, a flip-chip integrated circuit die having circuitry in a circuit side opposite a back side is formed having a back side including a thermal conductivity enhancing material. The thermal conductivity enhancing material improves the heat dissipating characteristics of the die during operation and testing and helps to reduce or prevent overheating. An epitaxial layer of silicon is formed in the back side, and circuitry is constructed in the epitaxial layer. Pre-existing circuitry on the circuit side and the newly formed circuitry in the back side are electrically coupled. The back side circuitry is operated in conjunction with the circuit side circuitry during testing and operation, and is useful, for example, for replacing defective circuitry, modifying circuit operation, and/or providing stimuli to the circuit side circuitry. The thermal conductivity enhancing material dissipates the heat generated by the circuitry and reduces the risk of a thermal related breakdown of the die. This improves the ability to analyze the die under normal and above normal operating temperatures without necessarily causing a failure in the die.

摘要翻译： 使用用于提高半导体管芯的散热特性的系统和方法来增强半导体分析。 根据本发明的示例性实施例，形成具有在后侧相反的电路侧中的电路的倒装芯片集成电路管芯，其背面包括导热性增强材料。 导热性提高材料提高了操作和测试期间模具的散热特性，有助于减少或防止过热。 在外侧形成硅的外延层，在外延层中构成电路。 电路侧的预先存在的电路和后侧的新形成的电路电耦合。 在测试和操作期间，背面电路与电路侧电路一起操作，并且例如用于替换有缺陷的电路，修改电路操作和/或向电路侧电路提供刺激是有用的。 热导率增强材料消散了电路产生的热量，并降低了模具的热相关破坏的风险。 这提高了在正常和高于正常操作温度下分析模具的能力，而不一定导致模具故障。

公开(公告)号：US06518783B1

公开(公告)日：2003-02-11

申请号：US09864669

申请日：2001-05-23

申请人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone ,  Rama R. Goruganthu

发明人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone ,  Rama R. Goruganthu

IPC分类号： H01L2166

CPC分类号： G01R31/2884

摘要： According to an example embodiment of the present invention, a semiconductor die having a buried insulator layer between a circuit side and a back side is selectively thinned. During thinning, a selected portion of the bulk silicon layer on the back side is removed and a void created. A circuit is formed in the void and is coupled to the existing circuitry on the circuit side of the die. The new circuit is used to analyze the die during operation, testing, or other conditions. The newly formed circuit enhances the ability to analyze the semiconductor die by adding flexibility to the traditional analysis methods used for integrated circuit dice. The newly formed circuit enables many new ways of interactively using the existing circuitry some of which include replacement of defective circuitry, modification of existing circuit operations, and stimulation of existing circuitry for testing.

摘要翻译： 根据本发明的示例性实施例，选择性地减薄在电路侧和背面之间具有掩埋绝缘体层的半导体管芯。 在减薄期间，去除背面上的体硅层的选定部分并产生空隙。 在空隙中形成电路并且耦合到管芯电路侧上的现有电路。 新电路用于在运行，测试或其他条件下对芯片进行分析。 新形成的电路通过增加集成电路芯片的传统分析方法的灵活性，增强了半导体芯片的分析能力。 新形成的电路使得能够交互地使用现有电路的许多新方式，其中一些电路包括有缺陷电路的更换，现有电路操作的修改和用于测试的现有电路的刺激。

公开(公告)号：US06455334B1

公开(公告)日：2002-09-24

申请号：US09409982

申请日：1999-09-30

申请人： Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Glen Gilfeather

发明人： Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Glen Gilfeather

IPC分类号： H01L2166

CPC分类号： G01R31/2884 ,  Y10S438/977 ,  Y10S977/854

摘要： The ability to monitor virtually any portion of semiconductor device is enhanced via a grid formed for analyzing circuitry in the semiconductor device. According to an example embodiment of the present invention, a grid having a plurality of narrow probe points is formed extending over target circuitry in a semiconductor device. The grid is accessed and used for monitoring various target circuitry within the device by accessing the part of the grid that corresponds to the portion of the target circuitry to which access is desired.

摘要翻译： 通过形成用于分析半导体器件中的电路的栅格来增强对几乎任何部分的半导体器件的监视能力。 根据本发明的一个示例性实施例，在半导体器件中形成有延伸超过目标电路的具有多个窄探针点的格栅。 电网被访问并用于通过访问对应于期望接入的目标电路的部分的网格部分来监视设备内的各种目标电路。

公开(公告)号：US06417680B1

公开(公告)日：2002-07-09

申请号：US09408663

申请日：1999-09-29

申请人： Jeffrey D. Birdsley ,  Rama R. Goruganthu ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring

发明人： Jeffrey D. Birdsley ,  Rama R. Goruganthu ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring

IPC分类号： G01R3102

CPC分类号： G01R31/311

摘要： According to an example embodiment, a laser is directed at a target region of a powered semiconductor device via the back side of the device, and active circuitry is selectively excited. In response to the excited circuitry, target circuitry is monitored and a degree of integrity of the operation of the semiconductor device is determined, for example, by detecting the output s/phase characteristics or by monitoring passive emissions from the device. The invention is particularly advantageous in connection with post-manufacture failure analysis.

摘要翻译： 根据示例性实施例，激光器经由设备的背面被引导到有源半导体器件的目标区域，并且有选择地激励有源电路。 响应于激励电路，监视目标电路，并且例如通过检测输出s /相位特性或通过监视来自装置的被动发射来确定半导体器件的操作的完整程度。 本发明在制造后故障分析方面是特别有利的。

公开(公告)号：US06391664B1

公开(公告)日：2002-05-21

申请号：US09409302

申请日：1999-09-29

申请人： Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring

发明人： Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring

IPC分类号： H01L2100

CPC分类号： H01L31/068 ,  Y02E10/547

摘要： An integrated circuit manufacturing approach involves using a solar cell and facilitating post-manufacturing analysis. According to an example embodiment of the present invention, a solar cell is formed in an integrated circuit device and coupled to target circuitry in the device. The solar cell is activated and provides power to the target circuitry. In response to the solar cell providing power to the target circuitry, the integrated circuit is analyzed.

摘要翻译： 集成电路制造方法涉及使用太阳能电池并促进后期制造分析。 根据本发明的示例性实施例，太阳能电池形成在集成电路器件中并耦合到器件中的目标电路。 太阳能电池被激活并为目标电路提供电力。 响应于向目标电路提供电力的太阳能电池，分析集成电路。

公开(公告)号：US06387715B1

公开(公告)日：2002-05-14

申请号：US09409975

申请日：1999-09-30

申请人： Brennan V. Davis ,  Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Rosalinda M. Ring

发明人： Brennan V. Davis ,  Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Rosalinda M. Ring

IPC分类号： H01L2166

CPC分类号： H01L22/12 ,  G01N25/72

摘要： Defect detection for post-manufacturing analysis of an integrated circuit die is enhanced via a method and system that use IR thermography to detect defects in circuitry within the die. According to an example embodiment of the present invention, substrate is removed from an integrated circuit die and a target region is exposed. A portion of the target region is heated with an infrared (IR) laser beam, and the die is imaged using IR thermography. The image is compared with a reference image, and damage to the integrated circuit is detected therefrom.

摘要翻译： 通过使用IR热成像技术检测管芯内电路缺陷的方法和系统，增强了集成电路管芯后制造分析的缺陷检测。 根据本发明的示例性实施例，从集成电路管芯移除衬底并暴露目标区域。 用红外（IR）激光束加热目标区域的一部分，并使用红外热像仪对裸片进行成像。 将图像与参考图像进行比较，并从其检测到集成电路的损坏。