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74 条记录 (耗时 0.027 秒)

    Selective state change analysis of a SOI die
    1.
    发明授权
    Selective state change analysis of a SOI die 失效
    SOI裸片的选择状态变化分析

    公开(公告)号：US06414335B1

    公开(公告)日：2002-07-02

    申请号：US09864688

    申请日：2001-05-23

    申请人： Rama R. Goruganthu ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone ,  Jeffrey D. Birdsley

    发明人： Rama R. Goruganthu ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone ,  Jeffrey D. Birdsley

    IPC分类号： H01L2358

    CPC分类号： G01R31/312 ,  G01R31/307

    摘要： Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by capacitively coupling a signal to the die. According to an example embodiment of the present invention, a die having a thinned back side is analyzed by capacitively coupling an input signal through the insulator portion of the SOI structure and effecting a state change to circuitry in the die. The state change is used to evaluate a characteristic of the die, such as by detecting a response to the state change. The ability to force such a state change is helpful for evaluating dies having SOI structure, and is particularly useful for evaluation techniques that require or benefit from maintaining the insulator portion of the SOI structure intact.

    摘要翻译： 通过将信号电容耦合到管芯来增强具有绝缘体上硅（SOI）结构的半导体管芯的分析。 根据本发明的示例性实施例，通过电容耦合通过SOI结构的绝缘体部分的输入信号并对模具中的电路进行状态分析来分析具有减薄背侧的管芯。 状态变化用于评估管芯的特性，例如通过检测对状态变化的响应。 强制这种状态变化的能力有助于评估具有SOI结构的管芯，并且对于需要或受益于保持SOI结构的绝缘体部分而完整的评估技术特别有用。

    Circuit construction in back side of die and over a buried insulator
    2.
    发明授权
    Circuit construction in back side of die and over a buried insulator 失效
    模具背面的电路结构和埋地绝缘子上方

    公开(公告)号：US06518783B1

    公开(公告)日：2003-02-11

    申请号：US09864669

    申请日：2001-05-23

    申请人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone ,  Rama R. Goruganthu

    发明人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone ,  Rama R. Goruganthu

    IPC分类号： H01L2166

    CPC分类号： G01R31/2884

    摘要： According to an example embodiment of the present invention, a semiconductor die having a buried insulator layer between a circuit side and a back side is selectively thinned. During thinning, a selected portion of the bulk silicon layer on the back side is removed and a void created. A circuit is formed in the void and is coupled to the existing circuitry on the circuit side of the die. The new circuit is used to analyze the die during operation, testing, or other conditions. The newly formed circuit enhances the ability to analyze the semiconductor die by adding flexibility to the traditional analysis methods used for integrated circuit dice. The newly formed circuit enables many new ways of interactively using the existing circuitry some of which include replacement of defective circuitry, modification of existing circuit operations, and stimulation of existing circuitry for testing.

    摘要翻译： 根据本发明的示例性实施例，选择性地减薄在电路侧和背面之间具有掩埋绝缘体层的半导体管芯。 在减薄期间，去除背面上的体硅层的选定部分并产生空隙。 在空隙中形成电路并且耦合到管芯电路侧上的现有电路。 新电路用于在运行，测试或其他条件下对芯片进行分析。 新形成的电路通过增加集成电路芯片的传统分析方法的灵活性，增强了半导体芯片的分析能力。 新形成的电路使得能够交互地使用现有电路的许多新方式，其中一些电路包括有缺陷电路的更换，现有电路操作的修改和用于测试的现有电路的刺激。

    Defect detection in semiconductor devices
    3.
    发明授权
    Defect detection in semiconductor devices 失效
    半导体器件缺陷检测

    公开(公告)号：US06686757B1

    公开(公告)日：2004-02-03

    申请号：US09409217

    申请日：1999-09-30

    申请人： Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis ,  Jeffrey D. Birdsley ,  Michael R. Bruce

    发明人： Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis ,  Jeffrey D. Birdsley ,  Michael R. Bruce

    IPC分类号： G01R3128

    CPC分类号： G01R31/311

    摘要： According to an example embodiment of the present invention, a defect detection approach involves detecting the existence of defects in an integrated circuit as a function of at least one applied energy source. In response to energy that is applied to the integrated circuit, response signals are detected. A parameter including information such as amplitude, frequency, phase, or a spectrum is developed for a reference integrated circuit device and then compared to the detected response signal. The deviation in the response and reference signals, and the type of energy source used, are correlated to a particular defect in the device.

    摘要翻译： 根据本发明的示例性实施例，缺陷检测方法包括检测作为至少一个应用能量源的函数的集成电路中的缺陷的存在。 响应于施加到集成电路的能量，检测响应信号。 为参考集成电路器件开发包括振幅，频率，相位或频谱等信息的参数，然后与检测到的响应信号进行比较。 响应和参考信号的偏差以及所使用的能量源的类型与设备中的特定缺陷相关。

    Quadrant avalanche photodiode time-resolved detection
    4.
    发明授权
    Quadrant avalanche photodiode time-resolved detection 失效
    象限雪崩光电二极管时间分辨检测

    公开(公告)号：US06483327B1

    公开(公告)日：2002-11-19

    申请号：US09409088

    申请日：1999-09-30

    申请人： Michael R. Bruce ,  Victoria J. Bruce ,  Jeffrey D. Birdsley ,  Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis

    发明人： Michael R. Bruce ,  Victoria J. Bruce ,  Jeffrey D. Birdsley ,  Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis

    IPC分类号： G01R31302

    CPC分类号： G01R1/071 ,  G01R31/311

    摘要： A method and system providing spatial and timing resolution for photoemission microscopy of an integrated circuit. A microscope having an objective lens forming a focal plane is arranged to view the integrated circuit, and an aperture element having an aperture is optically aligned in the back focal plane of the microscope. The aperture element is positioned for viewing a selected area of the integrated circuit. A position-sensitive avalanche photo-diode is optically aligned with the aperture to detect photoemissions when test signals are applied to the integrated circuit.

    摘要翻译： 一种为集成电路的光电显微镜提供空间和时序分辨率的方法和系统。 具有形成焦平面的物镜的显微镜被布置成观看集成电路，并且具有孔的孔径元件在显微镜的后焦平面中被光学对准。 光圈元件被定位成用于观看集成电路的选定区域。 位置敏感的雪崩光电二极管与孔径光学对准以在测试信号被施加到集成电路时检测光电发射。

    Acoustic 3D analysis of circuit structures
    5.
    发明授权
    Acoustic 3D analysis of circuit structures 失效
    电路结构的声学3D分析

    公开(公告)号：US06430728B1

    公开(公告)日：2002-08-06

    申请号：US09410147

    申请日：1999-09-30

    申请人： Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring

    发明人： Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring

    IPC分类号： G06F1750

    CPC分类号： G01R31/307 ,  G10K15/046

    摘要： According to an example embodiment, the present invention is directed to a system and method for analyzing an integrated circuit. A laser is directed to the back side of an integrated circuit and causes local heating, which generates acoustic energy in the circuit. The acoustic energy propagation in the integrated circuit is detected via at least two detectors. Using the detected acoustic energy from the detectors, at least one circuit defect is detected and located.

    摘要翻译： 根据示例性实施例，本发明涉及用于分析集成电路的系统和方法。 激光被引导到集成电路的背面，并引起局部加热，其在电路中产生声能。 通过至少两个检测器检测集成电路中的声能传播。 使用来自检测器的检测到的声能，检测和定位至少一个电路缺陷。

    Substrate removal as a functional of sonic analysis
    7.
    发明授权
    Substrate removal as a functional of sonic analysis 失效
    基底去除作为声波分析的函数

    公开(公告)号：US06350624B1

    公开(公告)日：2002-02-26

    申请号：US09409304

    申请日：1999-09-29

    申请人： Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring

    发明人： Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring

    IPC分类号： H01L21302

    CPC分类号： G01N1/32 ,  G01R31/311

    摘要： Substrate removal for post-manufacturing analysis of a semiconductor device is enhanced via a method and system that use sonic energy in the control of the removal process. According to an example embodiment of the present invention, sonic energy is reflected off of a region of a semiconductor chip having a portion of substrate removed from the back side of the chip. The reflections are detected and used to determine the thickness of substrate in the back side. In this manner, the substrate removal process can be efficiently and accurately controlled.

    摘要翻译： 通过在控制去除过程中使用声能的方法和系统来增强用于半导体器件后制造分析的衬底去除。 根据本发明的示例性实施例，声能被从芯片的背面去除的衬底的一部分的半导体芯片的区域反射出来。 检测反射并用于确定背面底物的厚度。 以这种方式，可以有效且准确地控制基板去除处理。