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    Apparatus and method for maintaining processing consistency in a computer system having multiple processors
    14.
    发明授权
    Apparatus and method for maintaining processing consistency in a computer system having multiple processors 失效
    用于在具有多个处理器的计算机系统中维持处理一致性的装置和方法

    公开(公告)号：US5420991A

    公开(公告)日：1995-05-30

    申请号：US177239

    申请日：1994-01-04

    申请人： Kris G. Konigsfeld ,  Jeffrey M. Abramson ,  Haitham Akkary ,  Glenn J. Hinton ,  Andrew F. Glew

    发明人： Kris G. Konigsfeld ,  Jeffrey M. Abramson ,  Haitham Akkary ,  Glenn J. Hinton ,  Andrew F. Glew

    IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F12/08 ,  G06F9/46

    CPC分类号： G06F9/30043 ,  G06F12/0831 ,  G06F9/3834

    摘要： An apparatus for maintaining processor ordering in a multi-processor computer system wherein loads are performed speculatively. Speculative loads of each processor are temporarily stored in their respective processors' load buffer. When one of the processors performs a store, a snoop operation is performed on the other processors' load buffers. If the snoop results in a hit, a determination is made as to whether that load buffer contains any prior conflicting speculative loads which have been completed. If the load buffer does contain a prior conflicting load, a processor ordering violation signal is generated. In response to this signal, the violating load and all subsequent operations are canceled and re-executed at a later time.

    摘要翻译： 一种用于在多处理器计算机系统中维持处理器排序的装置，其中负载被推测地执行。 每个处理器的推测负载临时存储在它们各自的处理器的负载缓冲器中。 当其中一个处理器执行存储时，对其他处理器的负载缓冲区执行窥探操作。 如果窥探导致命中，则确定该加载缓冲器是否包含已经完成的任何先前冲突的推测负载。 如果加载缓冲区确实包含先前存在冲突的负载，则会生成处理器排序违规信号。 响应于该信号，违反负载和所有后续操作将在以后被取消并重新执行。

    Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations
    18.
    发明授权
    Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations 失效
    具有处理推测性调度负载操作的内存子系统的乱序处理器

    公开(公告)号：US5751983A

    公开(公告)日：1998-05-12

    申请号：US538594

    申请日：1995-10-03

    申请人： Jeffrey M. Abramson ,  David B. Papworth ,  Haitham H. Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland

    发明人： Jeffrey M. Abramson ,  David B. Papworth ,  Haitham H. Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland

    IPC分类号： G06F9/38 ,  G06F3/38

    CPC分类号： G06F9/3834

    摘要： A method and apparatus for speculatively dispatching and/or executing LOADs in a computer system includes a memory subsystem of a out-of-order processor that handles LOAD and STORE operations by dispatching them to respective LOAD and STORE buffers in the memory subsystem. When a LOAD is subsequently dispatched for execution, the store buffer is searched for STOREs having unknown addresses. If any STOREs are found which are older than the dispatched LOAD, and which have an unknown address, the LOAD is tagged with an unknown STORE address identification (USAID). When a STORE is dispatched for execution, the LOAD buffer is searched for loads that have been denoted as mis-speculated loads. Mis-speculated loads are prevented from corrupting the architectural state of the machine with invalid data.

    摘要翻译： 用于在计算机系统中推测调度和/或执行LOAD的方法和装置包括无序处理器的存储器子系统，其通过将它们分派到存储器子系统中的相应LOAD和STORE缓冲器来处理LOAD和STORE操作。 当随后调度LOAD进行执行时，搜索具有未知地址的STORE的存储缓冲区。 如果发现任何比发送的LOAD更旧的存储区，并且具有未知地址，则LOAD被标记为未知的存储地址标识（USAID）。 当调度STORE执行时，LOAD缓冲区将搜索已被表示为误推测负载的负载。 可以防止误导的负载破坏机器的无效数据的架构状态。

    Method and apparatus for saving the effective address of floating point memory operations in an out-of-order microprocessor
    20.
    发明授权
    Method and apparatus for saving the effective address of floating point memory operations in an out-of-order microprocessor 失效
    用于将浮点存储器操作的有效地址保存在无序微处理器中的方法和装置

    公开(公告)号：US5721857A

    公开(公告)日：1998-02-24

    申请号：US651506

    申请日：1996-05-22

    申请人： Andrew F. Glew ,  Jeffrey M. Abramson ,  Kris G. Konigsfeld ,  Atiq Bajwa ,  Warren R. Morrow ,  William C. Alexander, III

    发明人： Andrew F. Glew ,  Jeffrey M. Abramson ,  Kris G. Konigsfeld ,  Atiq Bajwa ,  Warren R. Morrow ,  William C. Alexander, III

    IPC分类号： G06F9/38 ,  G06F9/26 ,  G06F12/00 ,  G06F12/10

    CPC分类号： G06F9/3861 ,  G06F9/3834

    摘要： A method is provided for recovering the effective address of memory instructions in an out-of-order microprocessor for use by an exception handler upon the occurrence of one of an exception and a systems management interrupt. The microprocessor comprises at least one execution unit for executing a plurality of instructions out-of-order and a re-order buffer having storage locations for buffering result data produced from the execution of the plurality of instructions. Each instruction is associated with a location designator to identify a unique storage location within the re-order buffer in which the result data for an executed instruction is written. The microprocessor further comprises a memory order buffer having storage locations for buffering memory instructions waiting for access to memory for execution, these storage locations also being identified by corresponding location designators. According to this embodiment of the microprocessor, the effective address of memory instructions can be reconstructed by utilizing the location designators of the ROB (Reorder Buffer) to find the corresponding storage location in the MOB (Memory Order Buffer) at which place the linear address for the instruction may be found. By associating both the retirement and exception information of the memory instructions stored within the storage locations of the re-order buffer with the corresponding memory instructions and information stored within the memory order buffer, the linear address of either the youngest, valid, retiring memory uop or the oldest, valid, excepted memory uop can be selected, written to memory and subsequently used to reconstruct the effective address of the memory instruction for use by an exception handler.

    摘要翻译： 提供了一种用于在异常处理器发生异常和系统管理中断之一时由异常处理器恢复无序微处理器中的存储器指令的有效地址的方法。 微处理器包括用于执行无序的多个指令的至少一个执行单元和具有用于缓冲从多个指令的执行产生的结果数据的存储位置的重新排序缓冲器。 每个指令与位置指示符相关联，以识别在其中写入执行指令的结果数据的重新排序缓冲器内的唯一存储位置。 微处理器还包括具有用于缓冲等待存储器进行执行的存储器指令的存储位置的存储器顺序缓冲器，这些存储位置也由对应的位置指示符标识。 根据微处理器的这个实施例，存储器指令的有效地址可以通过使用ROB（重排序缓冲器）的位置指示符来重建，以在MOB（存储器顺序缓冲器）中找到相应的存储位置， 可能会发现该指令。 通过将存储在重新排序缓冲器的存储位置中的存储器指令的退出和异常信息与存储在存储器顺序缓冲器中的相应存储器指令和信息相关联，最小的，有效的退出存储器存储器的线性地址 或者可以选择最旧的，有效的，例外的存储器，写入存储器，随后用于重建由异常处理程序使用的存储器指令的有效地址。