公开(公告)号：US06694400B1

公开(公告)日：2004-02-17

申请号：US09451121

申请日：1999-11-30

申请人： Jiin Lai ,  Chau-Chad Tsai ,  Chen-Ping Yang ,  Sheng-Chang Peng ,  Tse-Hsien Wang

发明人： Jiin Lai ,  Chau-Chad Tsai ,  Chen-Ping Yang ,  Sheng-Chang Peng ,  Tse-Hsien Wang

IPC分类号： G06F1338

CPC分类号： G06F13/4217

摘要： A method of conducting delayed data transaction on a PCI system and its associated devices. The delayed data transaction is carried out using a PCI system to transmit data between an initiator and a responder. Both the initiator and the responder are coupled to a PCI bus. The delayed transaction in the PCI system includes a number of steps. To begin with, the initiator will send out a request to use the PCI bus so that data transmission can be conducted with respect to the responder. If the responder accepts the request but unable to secure the requested data soon enough, the responder will generate a defer identifier that corresponds to the requesting initiator. Next, a stop signal and the defer identifier generated by the responder will be returned to the initiator, indicating that the request has been accepted. When the requested data is ready in the responder, the responder will forward the defer identifier again. The initiator picks up the defer identifier and prepares according to the buffer identifier in it. Then, data transmission between the initiator and the responder begins.

摘要翻译： 在PCI系统及其相关设备上进行延迟数据交易的方法。 延迟数据事务使用PCI系统在启动器和应答器之间传输数据。 启动器和应答器都与PCI总线相连。 PCI系统中的延迟事务包括多个步骤。 首先，启动器将发出使用PCI总线的请求，以便可以对响应者进行数据传输。 如果响应者接受请求但不能足够快地保护所请求的数据，则响应者将生成对应于请求的发起者的延迟标识符。 接下来，由响应者生成的停止信号和延迟标识符将被返回给启动器，指示该请求已被接受。 当请求的数据在响应者中准备就绪时，响应者将再次转发延迟标识符。 发起人拿起延迟标识符，并根据缓冲区标识符进行准备。 然后，启动器和应答器之间的数据传输开始。

公开(公告)号：US06687320B1

公开(公告)日：2004-02-03

申请号：US09322072

申请日：1999-05-27

申请人： You-Ming Chiu ,  Jiin Lai ,  Jyhfong Lin ,  Hsin-Chieh Lin ,  Wei-Yu Wang

发明人： You-Ming Chiu ,  Jiin Lai ,  Jyhfong Lin ,  Hsin-Chieh Lin ,  Wei-Yu Wang

IPC分类号： H03D324

CPC分类号： H03L7/081 ,  G06F1/08 ,  G06F1/10 ,  H03L7/18

摘要： A phase lock loop (PLL) clock generator with programmable frequency and skew is provided in the present invention, in which frequency of clock signals generated can be dynamically changed and skew of the clock signals generated can be dynamically adjusted by a computer program. Also, the signal skew due to the change of loading can be compensated. Therefore, the PLL clock generator based on a closed-loop configuration can better control the skew of clock signals to provide higher stability and durability to the system.

摘要翻译： 在本发明中提供了具有可编程频率和偏斜的锁相环（PLL）时钟发生器，其中产生的时钟信号的频率可以被动态地改变，并且可以通过计算机程序动态地调整产生的时钟信号的偏移。 此外，可以补偿由于负载变化引起的信号偏移。 因此，基于闭环配置的PLL时钟发​​生器可以更好地控制时钟信号的偏斜，为系统提供更高的稳定性和耐久性。

公开(公告)号：US06549964B1

公开(公告)日：2003-04-15

申请号：US09451820

申请日：1999-11-30

申请人： Jiin Lai ,  Chau-Chad Tsai ,  Chen-Ping Yang ,  Sheng-Chang Peng ,  Tse-Hsien Wang

发明人： Jiin Lai ,  Chau-Chad Tsai ,  Chen-Ping Yang ,  Sheng-Chang Peng ,  Tse-Hsien Wang

IPC分类号： G06F1300

CPC分类号： G06F13/4226

摘要： A delayed transaction method and system to handle multiple delayed transactions in a PCI system is disclosed. When the responder accepts a first and second request from an initiator but can not immediately respond to the first and second request, the responder generates a first and a second defer identifier corresponding to the initiator, respectively. When data transfer between the responder and the initiator corresponding to the first request is completed and data is ready for transfer corresponding to the second request, the responder immediately issues a second buffer identifier along with the data requested corresponding to the second request. Thus, data transfer between the initiator and the responder based on the second buffer identifier corresponding to the second request can proceed.

公开(公告)号：US06463013B1

公开(公告)日：2002-10-08

申请号：US09631293

申请日：2000-08-02

申请人： Kuo-Ping Liu ,  Jiin Lai ,  Jyh-fong Lin ,  Yu-Wei Lin

发明人： Kuo-Ping Liu ,  Jiin Lai ,  Jyh-fong Lin ,  Yu-Wei Lin

IPC分类号： G04F500

CPC分类号： H03L7/199 ,  G06F1/06 ,  H03L7/07 ,  H03L7/23

摘要： A clock generating apparatus and method for generating clock signals of different frequency. The clock generating apparatus and method receives and divides a main clock signal to obtain a reference clock signal. Then, the reference clock signal and the first feedback clock signal are phase-locked to obtain the first clock signal. Moreover, the reference clock signal and the second feedback clock signal are phase-locked to obtain the second clock signal. The reset signal and the first clock signal are received by a divider. The divider then outputs the first feedback clock signal. Another divider receives the reset signal and the second clock signal and then outputs the second feedback clock signal.

摘要翻译： 一种用于产生不同频率的时钟信号的时钟产生装置和方法。 时钟发生装置和方法接收和分割主时钟信号以获得参考时钟信号。 然后，参考时钟信号和第一反馈时钟信号被锁相以获得第一时钟信号。 此外，参考时钟信号和第二反馈时钟信号被锁相以获得第二时钟信号。 复位信号和第一时钟信号由分频器接收。 然后分频器输出第一反馈时钟信号。 另一分频器接收复位信号和第二时钟信号，然后输出第二反馈时钟信号。

公开(公告)号：US06400197B2

公开(公告)日：2002-06-04

申请号：US09766952

申请日：2001-01-22

申请人： Jiin Lai ,  Hsin-Chieh Lin ,  Kuo-Ping Liu

发明人： Jiin Lai ,  Hsin-Chieh Lin ,  Kuo-Ping Liu

IPC分类号： H03L700

CPC分类号： G06F5/06 ,  G06F1/10 ,  G06F2205/104 ,  H03L7/0814

摘要： A signal delay device having an internal delay lock loop for calibrating the delay interval. The signal delay device receives an input signal and then outputs the signal after a pre-defined delay period. The input signal varies according to a reference clock signal, and the required delay period is a quarter cycle of the clock signal. The delay device includes a multiplexer, an inverter, a phase detector, a counter and a delay element. During calibration, the phase detector, the counter and the delay element form a delay lock loop that can set up the delay time automatically.

摘要翻译： 一种具有用于校准延迟间隔的内部延迟锁定环路的信号延迟装置。 信号延迟装置接收输入信号，然后在预定义的延迟周期之后输出信号。 输入信号根据参考时钟信号而变化，所需的延迟周期是时钟信号的四分之一周期。 延迟装置包括多路复用器，反相器，相位检测器，计数器和延迟元件。 在校准期间，相位检测器，计数器和延迟元件形成可以自动设置延迟时间的延迟锁定环。

公开(公告)号：US06292521B1

公开(公告)日：2001-09-18

申请号：US09150365

申请日：1998-09-09

申请人： Jiin Lai ,  Hsin-Chieh Lin ,  Fang-Yi Chen

发明人： Jiin Lai ,  Hsin-Chieh Lin ,  Fang-Yi Chen

IPC分类号： H04L700

CPC分类号： H04L7/0338 ,  H03L7/0805 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0033

摘要： A phase lock device and method applicable to a data transmission system, particularly to a high speed transmission system are provided. Based on that the optimum operation margin for delaying data strobe is to shift the edge of data strobe to the middle region of data signal, the phase lock device and method suggest a solution, by analyzing the influence of environmental and operational conditions on delaying data strobe and system clock, to adapt delay element to the variation of environmental and operational conditions, so that the delay of data strobe is always in such a range that the data receiver can be enabled to do accurate and reliable data reading, regardless of external interference.

摘要翻译： 提供一种适用于数据传输系统，特别是高速传输系统的锁相装置和方法。 基于数据选通延迟的最佳运行余量是将数据选通的边沿移动到数据信号的中间区域，相位锁定装置和方法通过分析环境和运行条件对延迟数据选通的影响来提出解决方案 和系统时钟，以使延迟元件适应环境和操作条件的变化，使得数据选通的延迟总是处于使数据接收器能够进行精确和可靠的数据读取的范围，而不管外部干扰如何。

公开(公告)号：US06278641B1

公开(公告)日：2001-08-21

申请号：US09578234

申请日：2000-05-24

申请人： Chia-Hsin Chen ,  Jiin Lai

发明人： Chia-Hsin Chen ,  Jiin Lai

IPC分类号： G11C700

CPC分类号： G11C7/222 ,  G11C7/22 ,  G11C11/4076

摘要： An apparatus and method capable of programmably delaying a clock of a memory. The apparatus and method utilize the BIOS, external electric switches or other logic devices to selectively delay the clock of the DRAM and/or the internal clock of the north bridge, by which the DRAM has enough setup time at the rising edge of work clock to correctly read out the command word. The north bridge can then correctly receive data from the DRAM module and transfer the data to the CPU or AGP. Therefore, the memory can function normally even if the memory is operated at high speed or with heavy loading.

摘要翻译： 一种能够可编程地延迟存储器的时钟的装置和方法。 该装置和方法利用BIOS，外部电气开关或其他逻辑装置来选择性地延迟DRAM的时钟和/或北桥的内部时钟，由此DRAM在工作时钟的上升沿具有足够的建立时间 正确读出命令字。 然后，北桥可以从DRAM模块正确接收数据，并将数据传输到CPU或AGP。 因此，即使存储器以高速或大负载运行，存储器也能正常工作。

公开(公告)号：US08842983B2

公开(公告)日：2014-09-23

申请号：US12940347

申请日：2010-11-05

申请人： Jinkuan Tang ,  Jiin Lai ,  Hao-Hsuan Chiu

发明人： Jinkuan Tang ,  Jiin Lai ,  Hao-Hsuan Chiu

IPC分类号： H04B10/08 ,  H04B10/03

CPC分类号： H04B10/03

摘要： A data transmission system and method are provided. The data transmission system includes a first link partner and an optical transceiver unit. The first link partner includes a controller. When the first link partner is in an abnormal operation mode, the controller controls the first link partner to exit from the abnormal operation mode. The optical transceiver unit is coupled between the first link partner and a second link partner and performs data transmission between the first link partner and the second link partner. According to the data transmission system and method, one link partner can accurately detect whether another link partner is coupled to the one link partner through an optical transceiver unit. Accordingly, data transmission between the two link partners can be stably performed through the optical transceiver unit.

摘要翻译： 提供了一种数据传输系统和方法。 数据传输系统包括第一链路伙伴和光收发器单元。 第一个链路伙伴包括一个控制器。 当第一链路伙伴处于异常操作模式时，控制器控制第一链路伙伴退出异常操作模式。 光收发器单元耦合在第一链路伙伴和第二链路伙伴之间，并在第一链路伙伴和第二链路伙伴之间执行数据传输。 根据数据传输系统和方法，一个链路伙伴可以准确地检测另一个链路伙伴是否通过光收发器单元耦合到一个链路伙伴。 因此，可以通过光收发器单元稳定地执行两个链路伙伴之间的数据传输。

公开(公告)号：US08645630B2

公开(公告)日：2014-02-04

申请号：US12829345

申请日：2010-07-01

申请人： Xiu-Li Guo ,  Jiin Lai ,  Zhi-Qiang Hui ,  Shuang-Shuang Qin

发明人： Xiu-Li Guo ,  Jiin Lai ,  Zhi-Qiang Hui ,  Shuang-Shuang Qin

IPC分类号： G06F12/00

CPC分类号： G06F12/0862 ,  G06F12/0875 ,  G06F12/10 ,  G06F2212/6028

摘要： The present invention is directed to a stream context cache system, which primarily includes a cache and a mapping table. The cache stores plural stream contexts, and the mapping table stores associated stream context addresses in a system memory. Consequently, a host may, according to the content of the mapping table, directly retrieve the stream context that is pre-fetched and stored in the cache, rather than read the stream context from the system memory.

摘要翻译： 本发明涉及一种流上下文高速缓存系统，其主要包括高速缓存和映射表。 高速缓存存储多个流上下文，并且映射表将相关联的流上下文地址存储在系统存储器中。 因此，主机可以根据映射表的内容直接检索预取和存储在高速缓存中的流上下文，而不是从系统存储器读取流上下文。

公开(公告)号：US08572306B2

公开(公告)日：2013-10-29

申请号：US13089834

申请日：2011-04-19

申请人： Jiin Lai ,  Chin-Sung Hsu ,  Terrance Shiyang Shih ,  Jinkuan Tang ,  Buheng Xu ,  Hui Jiang

发明人： Jiin Lai ,  Chin-Sung Hsu ,  Terrance Shiyang Shih ,  Jinkuan Tang ,  Buheng Xu ,  Hui Jiang

IPC分类号： G06F13/36 ,  G06F13/40

CPC分类号： G06F13/4059 ,  G06F13/4291

摘要： The present invention is directed to a universal serial bus (USB) transaction translator and a micro-frame synchronization method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus, wherein the host USB version is higher than the device USB version. At least two buffers configured to store data are disposed between the device interface and the host interface. A controller stores the data in the buffers alternately. A start-of-frame (SOF) counter is used to count the SOF packets, wherein the counting value of the SOF counter is compared to a predefined value. Specifically, the controller resets a SOF timer for sending the SOF packet when the counting value achieves the predefined value or is greater than the predefined value, such that the SOF packet and an isochronous timestamp packet (ITP) from the host are sent at the same time. Further, the controller delays the sending of the SOF packet for a period of time according to the ITP from the host. In another embodiment, the sending period of SOF packets may be dynamically adjusted in isochronous transfer.

摘要翻译： 本发明涉及通用串行总线（USB）事务转换器和微帧同步方法。 设备接口经由设备总线耦合到设备，并且主机接口通过主机总线耦合到主机，其中主机USB版本高于设备USB版本。 配置为存储数据的至少两个缓冲器被布置在设备接口和主机接口之间。 控制器交替地将数据存储在缓冲器中。 使用起始帧（SOF）计数器对SOF分组进行计数，其中将SOF计数器的计数值与预定义的值进行比较。 具体地，当计数值达到预定义值或大于预定值时，控制器复位用于发送SOF分组的SOF定时器，使得来自主机的SOF分组和等时时间戳分组（ITP）以相同的方式发送 时间。 此外，控制器根据来自主机的ITP延迟SOF分组的发送一段时间。 在另一个实施例中，SOF分组的发送周期可以在等时传输中动态调整。