公开(公告)号：US20100200953A1

公开(公告)日：2010-08-12

申请号：US12766342

申请日：2010-04-23

申请人： Ethan H. Cannon ,  Alvin W. Strong

发明人： Ethan H. Cannon ,  Alvin W. Strong

IPC分类号： H01L29/86 ,  H01L21/26

CPC分类号： H01L23/345 ,  H01L2924/0002 ,  H01L2924/00

摘要： An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200° C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure.

摘要翻译： 片上加热器及其制造方法及其用途提供了加热器位于隔离区域内，隔离区域又位于半导体衬底内。 该加热器具有使半导体衬底能够或将其升高至至少约200℃的热输出。该加热器可用于对半导体结构内的电介质层内的俘获电荷进行热退火。

公开(公告)号：US08138573B2

公开(公告)日：2012-03-20

申请号：US12766342

申请日：2010-04-23

申请人： Ethan H. Cannon ,  Alvin W. Strong

发明人： Ethan H. Cannon ,  Alvin W. Strong

IPC分类号： H01L31/115

CPC分类号： H01L23/345 ,  H01L2924/0002 ,  H01L2924/00

摘要： An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200° C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure.

摘要翻译： 片上加热器及其制造方法及其用途提供了加热器位于隔离区域内，隔离区域又位于半导体衬底内。 该加热器具有使半导体衬底能够或将其升高至至少约200℃的热输出。该加热器可用于对半导体结构内的电介质层内的俘获电荷进行热退火。

公开(公告)号：US07704847B2

公开(公告)日：2010-04-27

申请号：US11419341

申请日：2006-05-19

申请人： Ethan H. Cannon ,  Alvin W. Strong

发明人： Ethan H. Cannon ,  Alvin W. Strong

IPC分类号： H01L21/762

CPC分类号： H01L23/345 ,  H01L2924/0002 ,  H01L2924/00

摘要： An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200° C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure.

摘要翻译： 片上加热器及其制造方法及其用途提供了加热器位于隔离区域内，隔离区域又位于半导体衬底内。 该加热器具有使半导体衬底能够或将其升高至至少约200℃的热输出。该加热器可用于对半导体结构内的电介质层内的俘获电荷进行热退火。

公开(公告)号：US07935609B2

公开(公告)日：2011-05-03

申请号：US12186750

申请日：2008-08-06

申请人： John M. Aitken ,  Ethan H. Cannon

发明人： John M. Aitken ,  Ethan H. Cannon

IPC分类号： H01L21/76

CPC分类号： H01L27/0688 ,  H01L21/2007 ,  H01L21/76264 ,  H01L21/8221 ,  H01L21/84

摘要： A method is provided for fabricating a semiconductor device and more particularly to a method of manufacturing a semiconductor device having radiation hardened buried insulators and isolation insulators in SOI technology. The method includes removing a substrate from an SOI wafer and selectively removing a buried oxide layer formed as a layer between the SOI wafer and active regions of a device. The method further comprises selectively removing isolation oxide formed between the active regions, and replacing the removed buried oxide layer and the isolation oxide with radiation hardened insulators.

摘要翻译： 提供一种用于制造半导体器件的方法，更具体地说，涉及在SOI技术中制造具有辐射硬化掩埋绝缘体和隔离绝缘体的半导体器件的方法。 该方法包括从SOI晶片去除衬底并选择性地去除在SOI晶片和器件的有源区之间形成为层的掩埋氧化物层。 该方法还包括选择性地去除在有源区之间形成的隔离氧化物，并用辐射硬化绝缘体代替去除的掩埋氧化物层和隔离氧化物。

公开(公告)号：US07943482B2

公开(公告)日：2011-05-17

申请号：US12186762

申请日：2008-08-06

申请人： John M. Aitken ,  Ethan H. Cannon

发明人： John M. Aitken ,  Ethan H. Cannon

IPC分类号： H01L21/76 ,  G06F17/50

CPC分类号： H01L23/556 ,  H01L21/76283 ,  H01L23/481 ,  H01L23/585 ,  H01L24/24 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/00

摘要： A design structure is provided for a semiconductor device having radiation hardened buried insulators and isolation insulators in SOI technology. The device includes a first structure and a second structure. The first structure includes: a radiation hardened BOX layer under an active device layer; radiation hardened shallow trench isolation (STI) structures between active regions of the active device layer and above the radiation hardened BOX layer; metal interconnects in one or more interlevel dielectric layers above gates structures of the active regions. The second structure is bonded to the first structure. The second structure includes: a Si based substrate; a BOX layer on the substrate; a Si layer with active regions on the BOX; oxide filled STI structures between the active regions of the Si layer; and metal interconnects in one or more interlevel dielectric layers above gates structures. At least one metal interconnect is electrically connecting the first structure to the second structure.

摘要翻译： 提供了一种在SOI技术中具有辐射硬化掩埋绝缘体和隔离绝缘体的半导体器件的设计结构。 该装置包括第一结构和第二结构。 第一结构包括：有源器件层下方的辐射硬化BOX层; 在有源器件层的有源区和辐射硬化BOX层之上的辐射硬化浅沟槽隔离（STI）结构; 在有源区域的栅极结构之上的一个或多个层间电介质层中的金属互连。 第二结构被结合到第一结构。 第二结构包括：基于硅的衬底; 衬底上的BOX层; BOX上有活性区的Si层; 在Si层的有源区之间的氧化物填充的STI结构; 以及栅极结构之上的一个或多个层间电介质层中的金属互连。 至少一个金属互连件将第一结构电连接到第二结构。

公开(公告)号：US20100035393A1

公开(公告)日：2010-02-11

申请号：US12186750

申请日：2008-08-06

申请人： John M. Aitken ,  Ethan H. Cannon

发明人： John M. Aitken ,  Ethan H. Cannon

IPC分类号： H01L21/8238 ,  H01L21/76

CPC分类号： H01L27/0688 ,  H01L21/2007 ,  H01L21/76264 ,  H01L21/8221 ,  H01L21/84

摘要： A method is provided for fabricating a semiconductor device and more particularly to a method of manufacturing a semiconductor device having radiation hardened buried insulators and isolation insulators in SOI technology. The method includes removing a substrate from an SOI wafer and selectively removing a buried oxide layer formed as a layer between the SOI wafer and active regions of a device. The method further comprises selectively removing isolation oxide formed between the active regions, and replacing the removed buried oxide layer and the isolation oxide with radiation hardened insulators.

摘要翻译： 提供一种用于制造半导体器件的方法，更具体地说，涉及在SOI技术中制造具有辐射硬化掩埋绝缘体和隔离绝缘体的半导体器件的方法。 该方法包括从SOI晶片去除衬底并选择性地去除在SOI晶片和器件的有源区之间形成为层的掩埋氧化物层。 该方法还包括选择性地去除在有源区之间形成的隔离氧化物，并用辐射硬化绝缘体代替去除的掩埋氧化物层和隔离氧化物。

公开(公告)号：US09223037B2

公开(公告)日：2015-12-29

申请号：US13442062

申请日：2012-04-09

申请人： Ethan H. Cannon ,  Michael J. Hauser ,  Timothy D. Sullivan

发明人： Ethan H. Cannon ,  Michael J. Hauser ,  Timothy D. Sullivan

IPC分类号： G01B5/28 ,  G01T5/02 ,  H01L23/556 ,  H01L27/146 ,  H01L23/00

CPC分类号： G01T5/02 ,  H01L23/556 ,  H01L24/16 ,  H01L27/14618 ,  H01L27/14636 ,  H01L2224/16225 ,  H01L2924/12032 ,  H01L2924/12043 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/00

摘要： Systems and methods to ensure correct operation of a semiconductor chip in the presence of ionizing radiation is disclosed. The system includes a semiconductor chip, a first radiation detection array incorporated in the semiconductor chip, and at least one additional radiation detection array incorporated in the semiconductor chip. a processor determines a region of the semiconductor chip affected by an incident radiation particle by analyzing a trajectory of the radiation particle determined from locations of sensors hit by the radiation particle in the first radiation detection array and the at least one additional radiation detection array. The processor determines whether corrective action is needed based on the region of the semiconductor chip affected by the incident radiation particle.

摘要翻译： 公开了在存在电离辐射的情况下确保半导体芯片的正确操作的系统和方法。 该系统包括半导体芯片，并入半导体芯片中的第一辐射检测阵列和并入半导体芯片中的至少一个附加辐射检测阵列。 处理器通过分析从第一辐射检测阵列中的辐射粒子和至少一个附加辐射检测阵列所击中的传感器的位置确定的辐射粒子的轨迹来确定受入射辐射粒子影响的半导体芯片的区域。 处理器基于受入射辐射粒子影响的半导体芯片的区域来确定是否需要校正动作。

公开(公告)号：US20110163365A1

公开(公告)日：2011-07-07

申请号：US13050052

申请日：2011-03-17

申请人： Ethan H. Cannon ,  Toshiharu Furukawa ,  David Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

发明人： Ethan H. Cannon ,  Toshiharu Furukawa ,  David Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

IPC分类号： H01L27/092 ,  H01L21/02

CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L27/0921 ,  H01L27/1104 ,  H01L29/66181 ,  H03K3/0375

摘要： A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).

摘要翻译： 数字逻辑存储结构包括形成在半导体衬底上的交叉耦合的第一和第二互补金属氧化物半导体（CMOS）反相器，所述CMOS反相器包括作为第一存储节点的逻辑补码的第一存储节点和第二存储节点; 第一和第二存储节点都通过开关晶体管选择性地耦合到深沟槽电容器，开关晶体管由耦合到其栅极导体的公共电容开关线控制; 其特征在于，在第一工作模式中，使开关晶体管变得不导通，从而将深沟槽电容器与逆变器存储节点隔离，并且在第二工作模式中，使开关晶体管导通，从而将深沟槽 电容器到其各自的存储节点，从而提供存储节点对单个事件扰乱（SEU）的增加的电阻。

公开(公告)号：US07965540B2

公开(公告)日：2011-06-21

申请号：US12055509

申请日：2008-03-26

申请人： Ethan H. Cannon ,  Toshiharu Furukawa ,  David Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

发明人： Ethan H. Cannon ,  Toshiharu Furukawa ,  David Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

IPC分类号： G11C11/412

CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L27/0921 ,  H01L27/1104 ,  H01L29/66181 ,  H03K3/0375

摘要： A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).

摘要翻译： 数字逻辑存储结构包括形成在半导体衬底上的交叉耦合的第一和第二互补金属氧化物半导体（CMOS）反相器，所述CMOS反相器包括作为第一存储节点的逻辑补码的第一存储节点和第二存储节点; 第一和第二存储节点都通过开关晶体管选择性地耦合到深沟槽电容器，开关晶体管由耦合到其栅极导体的公共电容开关线控制; 其特征在于，在第一工作模式中，使开关晶体管变得不导通，从而将深沟槽电容器与逆变器存储节点隔离，并且在第二工作模式中，使开关晶体管导通，从而将深沟槽 电容器到其各自的存储节点，从而提供存储节点对单个事件扰乱（SEU）的增加的电阻。

公开(公告)号：US09165917B2

公开(公告)日：2015-10-20

申请号：US12473409

申请日：2009-05-28

申请人： Ethan H. Cannon ,  David F. Heidel ,  K. Paul Muller ,  Alicia Wang

发明人： Ethan H. Cannon ,  David F. Heidel ,  K. Paul Muller ,  Alicia Wang

IPC分类号： H01L27/11 ,  H01L27/02 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L27/0207 ,  H01L21/823871 ,  H01L27/092

摘要： Each one of a pair of CMOS transistors is formed in its own island and a gate terminal for each transistor is formed by a single, in-line conductor connecting both gate terminals together. This type of “in-line” connection achieves nearly a five-time improvement in the reduction of the ability of ionizing radiation particles to strike both transistors at the same time as compared to prior art “side-by-side” transistor stacking through use of a relatively smaller solid angle spanning the two transistors. This results in “hardening” of the transistors and improving their resistance to single event upsets and, thus, improving the soft error rate (SER) of the transistors.

摘要翻译： 一对CMOS晶体管中的每一个形成在其自身的岛中，并且每个晶体管的栅极端子由连接两个栅极端子的单个直列导体形成。 与现有技术的“并排”晶体管堆叠通过使用相比，这种“在线”连接实现了与电离辐射颗粒同时撞击两个晶体管的能力的降低近乎五次的改进 具有跨越两个晶体管的相对较小的立体角。 这导致了晶体管的“硬化”，并提高了它们对单一事件的影响，从而提高了晶体管的软错误率（SER）。