利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

58 条记录 (耗时 0.038 秒)

    Loop circuitry with low-pass noise filter
    15.
    发明授权
    Loop circuitry with low-pass noise filter 失效
    具有低通噪声滤波器的回路电路

    公开(公告)号：US07002384B1

    公开(公告)日：2006-02-21

    申请号：US10759915

    申请日：2004-01-16

    申请人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Tzung-chin Chang

    发明人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Tzung-chin Chang

    IPC分类号： H03K5/13 ,  H03D3/24

    CPC分类号： H03L7/0814 ,  H03L7/085 ,  H03L7/093

    摘要： Phase comparators for use in loop circuits (i.e., DLL circuits and PLL circuits) are provided. The phase comparators include a phase detector for comparing a reference clock signal and a feedback signal derived from the loop circuit generated internal clock signal. The phase comparators also include a low-pass noise filter for filtering out erroneously detected phase differences between the reference clock signal and the feedback signal by requiring a certain net number of leading or lagging detections before the compensation circuitry of the loop circuit (i.e., the controlled delay line in a DLL circuit or the controlled oscillator in a PLL circuit) is adjusted. The number of net measurements required before these adjustments take place depends on a programmable bandwidth signal provided to the phase comparator.

    摘要翻译： 提供了用于环路电路（即DLL电路和PLL电路）的相位比较器。 相位比较器包括用于比较参考时钟信号和从产生的环路电路生成的内部时钟信号导出的反馈信号的相位检测器。 相位比较器还包括低通噪声滤波器，用于通过在环路电路的补偿电路之前需要一定的净数量的前导或滞后检测来滤除参考时钟信号和反馈信号之间的错误检测的相位差（即， 调节DLL电路中的受控延迟线或PLL电路中的受控振荡器）。 在进行这些调整之前所需的净测量数取决于提供给相位比较器的可编程带宽信号。

    Self-compensating delay chain for multiple-date-rate interfaces
    16.
    发明授权
    Self-compensating delay chain for multiple-date-rate interfaces 有权
    多速率接口的自补偿延迟链

    公开(公告)号：US07200769B1

    公开(公告)日：2007-04-03

    申请号：US10037861

    申请日：2002-01-02

    申请人： Yan Chong ,  Chiakang Sung ,  Bonnie I. Wang ,  Joseph Huang ,  Xiaobao Wang ,  Philip Pan ,  Tzung-Chin Chang

    发明人： Yan Chong ,  Chiakang Sung ,  Bonnie I. Wang ,  Joseph Huang ,  Xiaobao Wang ,  Philip Pan ,  Tzung-Chin Chang

    IPC分类号： G06F1/04

    CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C2207/108 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/091

    摘要： Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock signal and a first variable-delay block configured to receive an output from the frequency divider. Also included is a phase detector configured to receive the first clock signal and an output from the first variable-delay block, and an up/down counter configured to receive an output from the phase detector. A second variable-delay block is configured to receive a second clock signal and a plurality of flip-flops are configured to receive an output from the second variable-delay block. The first variable-delay block and the second variable-delay block are configured to receive an output from the up/down counter.

    摘要翻译： 用于延迟多数据速率接口的时钟信号的方法和装置。 一种装置提供一种集成电路，其包括配置成接收第一时钟信号的分频器和被配置为接收来自分频器的输出的第一可变延迟块。 还包括相位检测器，被配置为接收第一时钟信号和来自第一可变延迟块的输出，以及配置为接收来自相位检测器的输出的上/下计数器。 第二可变延迟块被配置为接收第二时钟信号，并且多个触发器被配置为从第二可变延迟块接收输出。 第一可变延迟块和第二可变延迟块被配置为从加/减计数器接收输出。

    Self-compensating delay chain for multiple-date-rate interfaces
    17.
    发明授权
    Self-compensating delay chain for multiple-date-rate interfaces 有权
    多速率接口的自补偿延迟链

    公开(公告)号：US07725755B1

    公开(公告)日：2010-05-25

    申请号：US11668353

    申请日：2007-01-29

    申请人： Yan Chong ,  Chiakang Sung ,  Bonnie I. Wang ,  Joseph Huang ,  Xiaobao Wang ,  Philip Pan ,  Tzung-Chin Chang

    发明人： Yan Chong ,  Chiakang Sung ,  Bonnie I. Wang ,  Joseph Huang ,  Xiaobao Wang ,  Philip Pan ,  Tzung-Chin Chang

    IPC分类号： G06F1/00 ,  G06F1/14

    CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C2207/108 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/091

    摘要： Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock signal and a first variable-delay block configured to receive an output from the frequency divider. Also included is a phase detector configured to receive the first clock signal and an output from the first variable-delay block, and an up/down counter configured to receive an output from the phase detector. A second variable-delay block is configured to receive a second clock signal and a plurality of flip-flops are configured to receive an output from the second variable-delay block. The first variable-delay block and the second variable-delay block are configured to receive an output from the up/down counter.

    摘要翻译： 用于延迟多数据速率接口的时钟信号的方法和装置。 一种装置提供一种集成电路，其包括配置成接收第一时钟信号的分频器和被配置为接收来自分频器的输出的第一可变延迟块。 还包括相位检测器，被配置为接收第一时钟信号和来自第一可变延迟块的输出，以及配置为接收来自相位检测器的输出的上/下计数器。 第二可变延迟块被配置为接收第二时钟信号，并且多个触发器被配置为从第二可变延迟块接收输出。 第一可变延迟块和第二可变延迟块被配置为从加/减计数器接收输出。

    Loop circuitry with low-pass noise filter
    18.
    发明授权
    Loop circuitry with low-pass noise filter 有权
    具有低通噪声滤波器的回路电路

    公开(公告)号：US07205806B2

    公开(公告)日：2007-04-17

    申请号：US11181366

    申请日：2005-07-13

    申请人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Tzung-chin Chang

    发明人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Tzung-chin Chang

    IPC分类号： H03K5/13 ,  H03D3/24

    CPC分类号： H03L7/0814 ,  H03L7/085 ,  H03L7/093

    摘要： Phase comparators for use in loop circuits (i.e., DLL circuits and PLL circuits) are provided. The phase comparators include a phase detector for comparing a reference clock signal and a feedback signal derived from the loop circuit generated internal clock signal. The phase comparators also include a low-pass noise filter for filtering out erroneously detected phase differences between the reference clock signal and the feedback signal by requiring a certain net number of leading or lagging detections before the compensation circuitry of the loop circuit (i.e., the controlled delay line in a DLL circuit or the controlled oscillator in a PLL circuit) is adjusted. The number of net measurements required before these adjustments take place depends on a programmable bandwidth signal provided to the phase comparator.

    摘要翻译： 提供了用于环路电路（即DLL电路和PLL电路）的相位比较器。 相位比较器包括用于比较参考时钟信号和从产生的环路电路生成的内部时钟信号导出的反馈信号的相位检测器。 相位比较器还包括低通噪声滤波器，用于通过在环路电路的补偿电路之前需要一定的净数量的前导或滞后检测来滤除参考时钟信号和反馈信号之间的错误检测的相位差（即， 调节DLL电路中的受控延迟线或PLL电路中的受控振荡器）。 在进行这些调整之前所需的净测量数取决于提供给相位比较器的可编程带宽信号。

    Loop circuitry with low-pass noise filter
    19.
    发明申请
    Loop circuitry with low-pass noise filter 有权

    公开(公告)号：US20060164139A1

    公开(公告)日：2006-07-27

    申请号：US11181366

    申请日：2005-07-13

    申请人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Tzung-chin Chang

    发明人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Tzung-chin Chang

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03L7/085 ,  H03L7/093

    摘要： Phase comparators for use in loop circuits (i.e., DLL circuits and PLL circuits) are provided. The phase comparators include a phase detector for comparing a reference clock signal and a feedback signal derived from the loop circuit generated internal clock signal. The phase comparators also include a low-pass noise filter for filtering out erroneously detected phase differences between the reference clock signal and the feedback signal by requiring a certain net number of leading or lagging detections before the compensation circuitry of the loop circuit (i.e., the controlled delay line in a DLL circuit or the controlled oscillator in a PLL circuit) is adjusted. The number of net measurements required before these adjustments take place depends on a programmable bandwidth signal provided to the phase comparator.

    Programmable high speed interface
    20.
    发明申请
    Programmable high speed interface 有权
    可编程高速接口

    公开(公告)号：US20060220703A1

    公开(公告)日：2006-10-05

    申请号：US11446483

    申请日：2006-06-02

    申请人： Bonnie Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

    发明人： Bonnie Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

    IPC分类号： H03B1/00

    CPC分类号： H03K19/17744 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/017581 ,  H03K19/1774 ,  H03K19/17788

    摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

    摘要翻译： 提供高速或低速灵活的输入和输出的方法和设备。 提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。 选择其中一个输入和输出电路，并取消选择其他电路。 高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。 低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。 这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。