公开(公告)号：US20240099027A1

公开(公告)日：2024-03-21

申请号：US18179895

申请日：2023-03-07

Applicant: Kioxia Corporation

Inventor： Kensuke TAKAHASHI ,  Daisaburo TAKASHIMA ,  Naoki KAI ,  Yasumi ISHIMOTO

IPC: H10B63/00 ,  H10B63/10

CPC classification number: H10B63/845 ,  H10B63/10 ,  H10B63/34

Abstract: According to one embodiment, a cell block includes memory cells and select transistors. The memory cells correspond are connected in parallel between a local source line and a local bit line. The select transistor is connected between the local bit line and a bit line. The memory cell includes a cell transistor and a resistance change element. A gate of the cell transistor is connected to a word line. The resistance change element is connected to the cell transistor in series between the local source line and the local bit line. Each cell block is configured as a columnar structure penetrating a plurality of conductive films functioning as word lines. The select transistor and the local bit line are connected at a contact portion formed of a material different from a material of the local bit line.

公开(公告)号：US20240038279A1

公开(公告)日：2024-02-01

申请号：US18359355

申请日：2023-07-26

Applicant: Kioxia Corporation

Inventor： Ryu OGIWARA ,  Hidehiro SHIGA ,  Daisaburo TAKASHIMA

IPC: G11C5/06 ,  G11C5/02 ,  H10B63/00

CPC classification number: G11C5/063 ,  G11C5/025 ,  H10B63/84 ,  H10B63/34

Abstract: According to one embodiment, in a semiconductor memory device, multiple first memory cells are connected in parallel between a first local bit line and a local source line. Multiple second memory cells are connected in parallel between a second local bit line and the local source line. Each of the multiple first memory cells includes a first cell transistor and a first resistance change element connected in series. Each of the multiple second memory cells includes a second cell transistor and a second resistance change element connected in series. A first selection gate line extends in a second direction across multiple cell blocks arranged in the second direction. A second selection gate line is placed on the opposite side of the first selection gate line with the local source line interposed therebetween. The second selection gate line extends in the second direction across multiple cell blocks arranged in the second direction.

公开(公告)号：US20210287743A1

公开(公告)日：2021-09-16

申请号：US17183803

申请日：2021-02-24

Applicant: KIOXIA CORPORATION

Inventor： Sumiko DOMAE ,  Daisaburo TAKASHIMA

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

Abstract: During a writing operation to change a resistance of a part of a variable resistance material film facing a first word line, the semiconductor storage device applies a first voltage to the first word line, applies a second voltage to a second word line, and applies a third voltage to a third word line. The first, second, and third word lines are stacked above a substrate. The second word line is adjacent to the first word line in the stacking direction. The third word line is not adjacent to the first word line in the stacking direction.

公开(公告)号：US20220393106A1

公开(公告)日：2022-12-08

申请号：US17679948

申请日：2022-02-24

Applicant: KIOXIA CORPORATION

Inventor： Masahiro TAKAHASHI ,  Yoshiaki ASAO ,  Yukihiro NOMURA ,  Daisaburo TAKASHIMA

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: A semiconductor storage device includes a memory cell including a core portion that extends in a first direction above a semiconductor substrate; a variable resistance layer that extends in the first direction and is in contact with the core portion; a semiconductor layer that extends in the first direction and is in contact with the variable resistance layer; a first insulator layer that extends in the first direction and is in contact with the semiconductor layer; and a first voltage applying electrode that extends in a second direction orthogonal to the first direction and is in contact with the first insulator layer. The core portion is a vacuum region, or a region containing inert gas.

公开(公告)号：US20220109024A1

公开(公告)日：2022-04-07

申请号：US17495103

申请日：2021-10-06

Applicant: Kioxia Corporation

Inventor： Ryu OGIWARA ,  Daisaburo TAKASHIMA ,  Takahiko IIZUKA

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: According to one embodiment, a memory device includes: a first variable resistance layer; first and second semiconductor layers being in contact with the first variable resistance layer; a first word line; a second word line being adjacent to the first word line; and a third word line being adjacent to the first and second word lines with the first semiconductor layer, the first variable resistance layer, and the second semiconductor layer interposed therebetween, and provided between the first word line and the second word line. In the first variable resistance layer, a first region including a shortest path connecting the first word line and the third word line functions as a first memory cell, and a second region including a shortest path connecting the third word line and the second word line functions as a second memory cell.

公开(公告)号：US20210399049A1

公开(公告)日：2021-12-23

申请号：US17348839

申请日：2021-06-16

Applicant: Kioxia Corporation

Inventor： Takahiko IIZUKA ,  Daisaburo TAKASHIMA ,  Ryu OGIWARA ,  Rieko FUNATSUKI ,  Yoshiki KAMATA ,  Misako MOROTA ,  Yoshiaki ASAO ,  Yukihiro NOMURA

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.

公开(公告)号：US20210090647A1

公开(公告)日：2021-03-25

申请号：US17022580

申请日：2020-09-16

Applicant: Kioxia Corporation

Inventor： Ryu OGIWARA ,  Daisaburo TAKASHIMA ,  Takahiko IIZUKA

IPC: G11C13/00

Abstract: According to one embodiment, a memory device includes a memory cell including a resistance change memory element in which a plurality of data values according to resistance are allowed to be set, and a selector element connected to the resistance change memory element in series, a word line supplying a select signal for selecting the resistance change memory element by the selector element to the memory cell, a bit line to which a data signal according to a data value set in the resistance change memory element is read, a load circuit connected to the memory cell in series and functioning as a load, and a comparator circuit which compares a voltage obtained by the load circuit with a plurality of reference voltages.

公开(公告)号：US20230284460A1

公开(公告)日：2023-09-07

申请号：US17899898

申请日：2022-08-31

Applicant: KIOXIA CORPORATION

Inventor： Tomoki CHIBA ,  Daisaburo TAKASHIMA ,  Hidehiro SHIGA

IPC: H01L27/24 ,  H01L27/22 ,  H01L45/00 ,  G11C11/16 ,  G11C13/00

CPC classification number: H01L27/2454 ,  H01L27/228 ,  H01L27/249 ,  H01L45/06 ,  H01L45/126 ,  H01L45/144 ,  H01L45/146 ,  H01L45/143 ,  G11C11/1673 ,  G11C13/004 ,  G11C2213/71

Abstract: A variable resistance non-volatile memory includes a semiconductor substrate, a first electrode line extending in a first direction away from the semiconductor substrate, a second electrode line extending in the first direction parallel to the first electrode line, an insulating film between the first and second electrode lines, a variable resistance film formed on the first electrode line, a low electrical resistance layer formed on the variable resistance film and having a lower electrical resistance than the variable resistance film, a semiconductor film in contact with the low electrical resistance layer and the insulating film, and formed on opposite surfaces of the second electrode line, a gate insulator film extending in the first direction and in contact with the semiconductor film, and a voltage application electrode that extends in a second direction that crosses the first direction, and is in contact with the gate insulator film.

公开(公告)号：US20230064982A1

公开(公告)日：2023-03-02

申请号：US17679959

申请日：2022-02-24

Applicant: KIOXIA CORPORATION

Inventor： Hidehiro SHIGA ,  Daisaburo TAKASHIMA

IPC: G11C13/00

Abstract: A memory device includes a memory cell array including a select transistor and a plurality of memory cells connected in series, each memory cell including a cell transistor and a variable resistance layer connected in parallel. During a write operation, a voltage setting circuit is controlled to apply a first voltage to a selected word line and a second voltage to non-selected word lines. The time period for applying the first voltage to the selected word line starts later than the time period for applying the second voltage to the non-selected word lines and ends earlier than the time period for applying the second voltage to the non-selected word lines.

公开(公告)号：US20220399400A1

公开(公告)日：2022-12-15

申请号：US17690387

申请日：2022-03-09

Applicant: Kioxia Corporation

Inventor： Daisaburo TAKASHIMA

IPC: H01L27/24 ,  H01L27/22

Abstract: According to one embodiment, in a nonvolatile semiconductor memory device, in a cell block, a local bit line is connected to a bit line via a select transistor. The local bit line extends in a third direction. A local source line is connected to a source line and extends in the third direction. A plurality of memory cells are connected in parallel between the local source line and the local bit line. Each of the memory cells includes a cell transistor and a resistance change element. The cell transistor has a gate connected to a corresponding one of the word lines and one end connected to one of the local bit line or the local source line. The resistance change element is connected between the other end of the cell transistor and the other one of the local bit line or the local source line.