公开(公告)号：US20240321352A1

公开(公告)日：2024-09-26

申请号：US18603281

申请日：2024-03-13

Applicant: Kioxia Corporation

Inventor： Ryu OGIWARA ,  Hidehiro SHIGA ,  Daisaburo TAKASHIMA

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0064

Abstract: According to one embodiment, a device includes: a memory cell coupled to a bit line and configured to store first data including first, second, and third bits; and a sense amplification circuit configured to perform a first comparison between a bit line voltage and a first reference voltage, and a second comparison between the bit line voltage and a second reference voltage lower than the first reference voltage, and to read the first data from the memory cell based on results of the first and second comparisons. The sense amplification circuit is configured to retain second data having a first code in response to the bit line voltage becoming equal to or lower than the first reference voltage during a first period from a start of operation to a first time point, and retain the first data after the first period.

公开(公告)号：US20230102229A1

公开(公告)日：2023-03-30

申请号：US17693935

申请日：2022-03-14

Applicant: Kioxia Corporation

Inventor： Yoshiki KAMATA ,  Yoshiaki ASAO ,  Yukihiro NOMURA ,  Misako MOROTA ,  Daisaburo TAKASHIMA ,  Takahiko IIZUKA ,  Shigeru KAWANAKA

IPC: G11C13/00 ,  G11C5/06 ,  H01L27/24 ,  H01L45/00

Abstract: According to one embodiment, a memory device includes a stacked structure including a plurality of conductive layers stacked to be apart from each other in a first direction, and a pillar structure including a resistance change portion extending in the first direction in the stacked structure, and a semiconductor portion which extends in the first direction in the stacked structure and which includes a first portion provided along the resistance change portion and a second portion extending from the first portion in at least one direction intersecting the first direction.

公开(公告)号：US20230065167A1

公开(公告)日：2023-03-02

申请号：US17681680

申请日：2022-02-25

Applicant: KIOXIA CORPORATION

Inventor： Tomoki CHIBA ,  Daisaburo TAKASHIMA ,  Hidehiro SHIGA

IPC: G11C13/00

Abstract: A nonvolatile memory includes a first memory cell and a second memory cell above the first memory cell. The first memory cell includes a variable resistance layer extending in a first direction, a semiconductor layer extending in the first direction and in contact with the variable resistance layer, an insulator layer extending in the first direction and in contact with the semiconductor layer, and a first voltage applying electrode extending in a second direction and in contact with the insulator layer. The second memory cell includes a second voltage applying electrode in contact with the insulator layer. When a write operation is performed on the first memory cell, a first voltage is applied to the second voltage applying electrode, and when a write operation is performed on the second memory cell, a second voltage, lower than the first voltage, is applied to the first voltage applying electrode.

公开(公告)号：US20220108729A1

公开(公告)日：2022-04-07

申请号：US17495747

申请日：2021-10-06

Applicant: Kioxia Corporation

Inventor： Ryu OGIWARA ,  Daisaburo TAKASHIMA ,  Takahiko IIZUKA

IPC: G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/10 ,  G11C5/06

Abstract: According to one embodiment, a memory device includes: a plurality of memory cells stacked in a first direction orthogonal to a substrate and each including a memory element having at least three resistance states and a selector coupled in parallel to the memory element; a bit line electrically coupled to the memory cells and extending in a second direction intersecting the first direction; and a sense amplifier configured to compare a voltage of the bit line with a plurality of reference voltages and sense data stored in the memory cells.

公开(公告)号：US20240049479A1

公开(公告)日：2024-02-08

申请号：US18177064

申请日：2023-03-01

Applicant: Kioxia Corporation

Inventor： Yuki ITO ,  Daisaburo TAKASHIMA ,  Hidehiro SHIGA ,  Yoshiki KAMATA

IPC: H10B63/00 ,  H10B61/00

CPC classification number: H10B63/845 ,  H10B63/34 ,  H10B61/22

Abstract: A variable resistance non-volatile memory includes a memory cell including a core portion extending in a first direction above a semiconductor substrate, a variable resistance layer extending in a first direction and in contact with the core portion, a semiconductor layer extending in a first direction and in contact with the variable resistance layer, an insulator layer extending in a first direction and in contact with the semiconductor layer, and a first voltage application electrode extending in a second direction crossing the first direction and in contact with the insulator layer. An impurity concentration of the semiconductor layer is non-uniform, such that an impurity concentration of a first portion of the semiconductor layer in contact with the insulator layer is at least ten times higher than an impurity concentration of a second portion of the semiconductor layer in contact with the variable resistance layer.

公开(公告)号：US20230413584A1

公开(公告)日：2023-12-21

申请号：US18231304

申请日：2023-08-08

Applicant: Kioxia Corporation

Inventor： Takahiko IIZUKA ,  Daisaburo TAKASHIMA ,  Ryu OGIWARA ,  Rieko FUNATSUKI ,  Yoshiki KAMATA ,  Misako MOROTA ,  Yoshiaki ASAO ,  Yukihiro NOMURA

IPC: H10B63/00 ,  G11C13/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/845 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C2213/75 ,  H10B63/34 ,  H10N70/066 ,  H10N70/231 ,  H10N70/8828 ,  G11C13/0069

Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.

公开(公告)号：US20230284464A1

公开(公告)日：2023-09-07

申请号：US17939859

申请日：2022-09-07

Applicant: Kioxia Corporation

Inventor： Hidehiro SHIGA ,  Daisaburo TAKASHIMA

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00 ,  H01L27/22 ,  H01L43/02 ,  G11C11/16

CPC classification number: H01L27/249 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/004 ,  G11C13/0069 ,  H01L27/228 ,  H01L27/2454 ,  H01L43/02 ,  H01L45/126 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/79

Abstract: According to a certain embodiment, the 3D stacked semiconductor memory includes: a first electrode line extending in a first direction orthogonal to the semiconductor substrate; a second electrode line adjacent to the first electrode line in a second direction orthogonal to the first direction, and extending in the first direction; a first variable resistance film extending in the first direction and in contact with the second electrode line; a first semiconductor film in contact with the first variable resistance film and the first electrode line; a first potential applying electrode extending in the second direction and in contact with a first insulator layer; a second semiconductor film in contact with a second variable resistance film and the first electrode line; and a second potential applying electrode extending in the second direction and in contact with a second insulator layer. The first and second potential applying electrodes are electrically different nodes.

公开(公告)号：US20220284953A1

公开(公告)日：2022-09-08

申请号：US17471981

申请日：2021-09-10

Applicant: Kioxia Corporation

Inventor： Daisaburo TAKASHIMA

IPC: G11C13/00

Abstract: According to one embodiment, there is provided a nonvolatile semiconductor memory device including a cell array. The cell array includes an array of a plurality of string blocks. Among the plurality of local string blocks, one local string block includes a block selection transistor and remaining local string blocks do not include a block selection transistor. A gate terminal of the block selection transistor of the one local string block is connected to a block selection line. Signals of two word lines connected to two adjacent string blocks in the bit line direction are common signals. Signals of two block selection lines connected to the two adjacent string blocks are independent of each other.

公开(公告)号：US20220028452A1

公开(公告)日：2022-01-27

申请号：US17443586

申请日：2021-07-27

Applicant: Kioxia Corporation

Inventor： Ryu OGIWARA ,  Daisaburo TAKASHIMA ,  Takahiko IIZUKA

IPC: G11C13/00 ,  G11C16/04 ,  G11C16/34

Abstract: According to one embodiment, a memory device includes: a variable resistance memory region; a semiconductor layer; an insulating layer; first and second word lines; and a first select gate line. When information stored in the first memory cell is read, or when information is written into the first memory cell, after a voltage of the first select gate line is set to a first voltage and voltages of the first and second word lines are set to a second voltage, the voltage of the first select gate line is increased from the first voltage to a third voltage. After the voltage of the first select gate line is increased to at least the second voltage, the voltage of the first word line is decreased from the second voltage to the first voltage, and the voltage of the second word line is increased from the second voltage to a fourth voltage.

公开(公告)号：US20240315052A1

公开(公告)日：2024-09-19

申请号：US18595323

申请日：2024-03-04

Applicant: Kioxia Corporation

Inventor： Daisaburo TAKASHIMA

IPC: H10B63/00 ,  H10B63/10

CPC classification number: H10B63/845 ,  H10B63/10 ,  H10B63/34

Abstract: A semiconductor storage device includes a stacked body having a plurality of conductive layers stacked in a stacking direction with an insulating layer interposed therebetween, and a columnar structure that extends in the stacking direction in the stacked body. The columnar structure has a variable-resistance film, a semiconductor film, an insulating film, and a resistor film, all of which extend in the stacking direction in the stacked body. The semiconductor film is between the variable-resistance film and the conductive layer. The insulating film is between the semiconductor film and the conductive layer. The resistor film is between the variable-resistance film and the semiconductor film. Memory cells are formed at locations where the conductive layers, the variable-resistance film, and the semiconductor film intersect. In each of the memory cells, the thickness of the resistor film is greater than the thickness of the variable-resistance film.