公开(公告)号：US20210073119A1

公开(公告)日：2021-03-11

申请号：US16807275

申请日：2020-03-03

Applicant: Kioxia Corporation

Inventor： Takehiko AMAKI ,  Toshikatsu HIDA ,  Shunichi IGAHARA ,  Yoshihisa KOJIMA ,  Suguru NISHIKAWA

IPC: G06F12/02 ,  G06F3/06

Abstract: According to one embodiment, a memory system includes a non-volatile memory including first and second block groups, and a controller that performs a first write operation for the first block group and the first or a second write operation for the second block group. A first or second number of bits is written into a memory cell in the first or the second write operation. The second number of bits is larger than the first number of bits. The controller allocates a block to a buffer as a write destination block in the first write operation based on a degree of wear-out of at least one block, and writes data from an external device into the buffer in the first write operation.

公开(公告)号：US20250077121A1

公开(公告)日：2025-03-06

申请号：US18820068

申请日：2024-08-29

Applicant: Kioxia Corporation

Inventor： Yuki KAWAGUCHI ,  Takehiko AMAKI ,  Suguru NISHIKAWA ,  Yoshihisa KOJIMA

IPC: G06F3/06

Abstract: A memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a memory cell and a control circuit that writes first data of n bits to the memory cell by a first write operation and writes second data of m bits, which includes the n bits of the first data, to the memory cell by a second write operation. The memory controller issues a first command sequence to the non-volatile memory to execute the first write operation, selects one of first and second methods for preparing the second data for the second write operation based on an index related to reliability of the first data stored in the memory cell, and issues a second command sequence to the non-volatile memory to execute the second write operation, the second command sequence indicating the selected method for preparing the second data.

公开(公告)号：US20230073249A1

公开(公告)日：2023-03-09

申请号：US17685229

申请日：2022-03-02

Applicant: KIOXIA CORPORATION

Inventor： Suguru NISHIKAWA ,  Toshikatsu HIDA ,  Shunichi IGAHARA ,  Takehiko AMAKI

IPC: G06F3/06

Abstract: According to one embodiment, a memory system includes non-volatile memory and volatile memory. A controller encodes a first unit size data portion to be written into the non-volatile memory and generates a first error correction code for the data portion, then writes the data portion into the non-volatile memory. The controller also stores the first error correction code in the volatile memory. When non-volatilization of an error correction code protect the data portion is requested, the controller encodes the data portion to generate a second error correction code for the data portion, and then writes the second error correction code into the non-volatile memory. The second error correction code is smaller in size than the first error correction code.

公开(公告)号：US20220058085A1

公开(公告)日：2022-02-24

申请号：US17519356

申请日：2021-11-04

Applicant: KIOXIA CORPORATION

Inventor： Shunichi IGAHARA ,  Yoshihisa KOJIMA ,  Takehiko AMAKI ,  Suguru NISHIKAWA

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory system includes a non-volatile memory and a controller that includes a toggle encoder configured to encode first data having a first bit length and a first number of toggles, into second data having a second bit length longer than the first bit length and a second number of toggles smaller than the first number of toggles, and transmit the second data to the non-volatile memory. The memory system may further include a toggle decoder configured to decode third data received from the non-volatile memory into fourth data, the third data having the second bit length and the second number of toggles and the fourth data having the first bit length and the first number of toggles.

公开(公告)号：US20210257027A1

公开(公告)日：2021-08-19

申请号：US17018147

申请日：2020-09-11

Applicant: Kioxia Corporation

Inventor： Suguru NISHIKAWA ,  Takehiko AMAKI ,  Yoshihisa KOJIMA ,  Shunichi IGAHARA

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34

Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.

公开(公告)号：US20210124529A1

公开(公告)日：2021-04-29

申请号：US17002173

申请日：2020-08-25

Applicant: Kioxia Corporation

Inventor： Suguru NISHIKAWA ,  Yoshihisa KOJIMA ,  Takehiko AMAKI

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34

Abstract: A memory system includes a memory device having a memory cell array, and a controller. The memory cell array includes a plurality of first units and at least one second unit. The second unit includes the plurality of first units. The controller counts a first number of times of read operation for each of the plurality of first units, and, in response to the first number of times for one first unit among the plurality of first units reaching a first value, updates a second number of times for the second unit that includes the one first unit. In response to the second number of times reaching a second value, the controller determines whether to rewrite data stored in at least one of the first units included in the second unit.

公开(公告)号：US20200303012A1

公开(公告)日：2020-09-24

申请号：US16799885

申请日：2020-02-25

Applicant: Kioxia Corporation

Inventor： Suguru NISHIKAWA ,  Riki SUZUKI ,  Yoshihisa KOJIMA

IPC: G11C16/16 ,  G11C16/26 ,  G11C16/12 ,  G11C16/34 ,  G06F13/16

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller that controls operation of the nonvolatile memory. The nonvolatile memory is configured to receive, from the memory controller, a first command for execution of at least one of an erase operation and a program operation; in response to receiving a second command from the memory controller during execution of a first operation requested by the first command, execute a second operation for suspending the first operation before the first operation reaches a given section; and in response to receiving a third command from the memory controller during the execution of the first operation, suspend the first operation after the given section.

公开(公告)号：US20250094336A1

公开(公告)日：2025-03-20

申请号：US18780618

申请日：2024-07-23

Applicant: Kioxia Corporation

Inventor： Suguru NISHIKAWA ,  Takehiko AMAKI ,  Shunichi IGAHARA ,  Toshikatsu HIDA ,  Yoshihisa KOJIMA

IPC: G06F12/02

Abstract: According to an embodiment, a memory system includes a nonvolatile memory including memory cells and a memory controller coupled to the nonvolatile memory. Each of the plurality of memory cells is configured to store, in a nonvolatile manner, a plurality of bits of data. The memory controller is configured to, in a case where a first memory cell stores valid first bit data as a first bit and does not store data as a second bit, and a second memory cell stores valid second bit data as the first bit and does not store data as the second bit, and upon reception of a flush command from a host, read the second bit data from the second memory cell and write the second bit data read from the second memory cell to the first memory cell as the second bit.

公开(公告)号：US20240096423A1

公开(公告)日：2024-03-21

申请号：US18177685

申请日：2023-03-02

Applicant: Kioxia Corporation

Inventor： Dongxiao YU ,  Masahiro KIYOOKA ,  Suguru NISHIKAWA ,  Yoshihisa KOJIMA

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/08 ,  G11C16/3459

Abstract: A memory system includes a semiconductor memory that includes a cell unit having a plurality of memory cells, and a control circuit for controlling the plurality of memory cells, and a memory controller configured to control the semiconductor memory. The control circuit is configured to execute a data read operation on the cell unit by using one or more read voltages, acquire first data by the data read operation, generate second data with a data size smaller than the first data, based on the first data, and transmit the second data to the memory controller. The memory controller is configured to determine, based on the second data, whether or not to rewrite the page data written in the cell unit.

公开(公告)号：US20230280943A1

公开(公告)日：2023-09-07

申请号：US18318078

申请日：2023-05-16

Applicant: Kioxia Corporation

Inventor： Suguru NISHIKAWA ,  Yoshihisa KOJIMA ,  Takehiko AMAKI

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0679 ,  G11C16/26 ,  G11C16/3427 ,  G11C16/0483 ,  G11C11/5642

Abstract: A memory system includes a memory device having a memory cell array, and a controller. The memory cell array includes a plurality of first units and at least one second unit. The second unit includes the plurality of first units. The controller counts a first number of times of read operation for each of the plurality of first units, and, in response to the first number of times for one first unit among the plurality of first units reaching a first value, updates a second number of times for the second unit that includes the one first unit. In response to the second number of times reaching a second value, the controller determines whether to rewrite data stored in at least one of the first units included in the second unit.