公开(公告)号：US11615851B2

公开(公告)日：2023-03-28

申请号：US17572279

申请日：2022-01-10

Applicant: Kioxia Corporation

Inventor： Suguru Nishikawa ,  Takehiko Amaki ,  Yoshihisa Kojima ,  Shunichi Igahara

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/08

Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.

公开(公告)号：US11422746B2

公开(公告)日：2022-08-23

申请号：US17002173

申请日：2020-08-25

Applicant: Kioxia Corporation

Inventor： Suguru Nishikawa ,  Yoshihisa Kojima ,  Takehiko Amaki

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04 ,  G11C11/56

Abstract: A memory system includes a memory device having a memory cell array, and a controller. The memory cell array includes a plurality of first units and at least one second unit. The second unit includes the plurality of first units. The controller counts a first number of times of read operation for each of the plurality of first units, and, in response to the first number of times for one first unit among the plurality of first units reaching a first value, updates a second number of times for the second unit that includes the one first unit. In response to the second number of times reaching a second value, the controller determines whether to rewrite data stored in at least one of the first units included in the second unit.

公开(公告)号：US11069413B2

公开(公告)日：2021-07-20

申请号：US16799885

申请日：2020-02-25

Applicant: Kioxia Corporation

Inventor： Suguru Nishikawa ,  Riki Suzuki ,  Yoshihisa Kojima

IPC: G11C16/16 ,  G11C16/26 ,  G06F13/16 ,  G11C16/34 ,  G11C16/12

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller that controls operation of the nonvolatile memory. The nonvolatile memory is configured to receive, from the memory controller, a first command for execution of at least one of an erase operation and a program operation; in response to receiving a second command from the memory controller during execution of a first operation requested by the first command, execute a second operation for suspending the first operation before the first operation reaches a given section; and in response to receiving a third command from the memory controller during the execution of the first operation, suspend the first operation after the given section.

公开(公告)号：US12086439B2

公开(公告)日：2024-09-10

申请号：US18343835

申请日：2023-06-29

Applicant: KIOXIA CORPORATION

Inventor： Shunichi Igahara ,  Toshikatsu Hida ,  Riki Suzuki ,  Takehiko Amaki ,  Suguru Nishikawa ,  Yoshihisa Kojima

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/10

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0253 ,  G06F12/10 ,  G06F2212/1044 ,  G06F2212/657

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.

公开(公告)号：US11740965B2

公开(公告)日：2023-08-29

申请号：US17519356

申请日：2021-11-04

Applicant: KIOXIA CORPORATION

Inventor： Shunichi Igahara ,  Yoshihisa Kojima ,  Takehiko Amaki ,  Suguru Nishikawa

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0679 ,  G06F11/1044 ,  G06F11/1056

Abstract: A memory system includes a non-volatile memory and a controller that includes a toggle encoder configured to encode first data having a first bit length and a first number of toggles, into second data having a second bit length longer than the first bit length and a second number of toggles smaller than the first number of toggles, and transmit the second data to the non-volatile memory. The memory system may further include a toggle decoder configured to decode third data received from the non-volatile memory into fourth data, the third data having the second bit length and the second number of toggles and the fourth data having the first bit length and the first number of toggles.

公开(公告)号：US11733888B2

公开(公告)日：2023-08-22

申请号：US17028087

申请日：2020-09-22

Applicant: Kioxia Corporation

Inventor： Shunichi Igahara ,  Toshikatsu Hida ,  Riki Suzuki ,  Takehiko Amaki ,  Suguru Nishikawa ,  Yoshihisa Kojima

IPC: G06F3/06 ,  G06F12/10 ,  G06F12/02

CPC classification number: G06F3/0634 ,  G06F3/061 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0253 ,  G06F12/10 ,  G06F2212/1044 ,  G06F2212/657

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.

公开(公告)号：US11342026B2

公开(公告)日：2022-05-24

申请号：US17018147

申请日：2020-09-11

Applicant: Kioxia Corporation

Inventor： Suguru Nishikawa ,  Takehiko Amaki ,  Yoshihisa Kojima ,  Shunichi Igahara

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26

Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.

公开(公告)号：US11194656B2

公开(公告)日：2021-12-07

申请号：US16774609

申请日：2020-01-28

Applicant: KIOXIA CORPORATION

Inventor： Shunichi Igahara ,  Yoshihisa Kojima ,  Takehiko Amaki ,  Suguru Nishikawa

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory system includes a non-volatile memory and a controller that includes a toggle encoder configured to encode first data having a first bit length and a first number of toggles, into second data having a second bit length longer than the first bit length and a second number of toggles smaller than the first number of toggles, and transmit the second data to the non-volatile memory. The memory system may further include a toggle decoder configured to decode third data received from the non-volatile memory into fourth data, the third data having the second bit length and the second number of toggles and the fourth data having the first bit length and the first number of toggles.

公开(公告)号：US12159061B2

公开(公告)日：2024-12-03

申请号：US18092158

申请日：2022-12-30

Applicant: Kioxia Corporation

Inventor： Marie Sia ,  Yoshihisa Kojima ,  Suguru Nishikawa ,  Riki Suzuki

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

Abstract: A memory system includes a non-volatile memory chip that includes a memory cell array, and a memory controller. The memory controller is configured to perform a read operation on the non-volatile memory chip by instructing the non-volatile memory chip to perform a sensing operation to read data stored in the memory cell array, estimating a time when the read data becomes ready to be transferred from the non-volatile memory chip to the memory controller, and instructing the non-volatile memory chip, after the estimated time, to perform a transfer operation to transfer the read data to the memory controller.

公开(公告)号：US11790997B2

公开(公告)日：2023-10-17

申请号：US17471569

申请日：2021-09-10

Applicant: Kioxia Corporation

Inventor： Tomoya Kamata ,  Yoshihisa Kojima ,  Suguru Nishikawa

IPC: G11C16/08 ,  G11C16/32 ,  G11C7/22

CPC classification number: G11C16/32 ,  G11C7/22

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to cause the nonvolatile memory to execute a first process of reading data based on a first request from a host device. The memory controller is configured to, when the first request is received from the host device while causing the nonvolatile memory to execute a second process, hold interruption of the second process until a first number becomes a first threshold value or more. The first number is a number of the first requests to be performed in the memory controller. The first threshold value is an integer of 2 or more.