公开(公告)号：US20240305279A1

公开(公告)日：2024-09-12

申请号：US18460030

申请日：2023-09-01

Applicant: Kioxia Corporation

Inventor： Toshifumi WATANABE ,  Kiyofumi SAKURAI ,  Teppei HIGASHITSUJI ,  Takumi KOSAKI ,  Eiji KOZUKA

IPC: H03K3/356 ,  G11C16/04 ,  G11C16/26 ,  G11C16/30

CPC classification number: H03K3/356017 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/30

Abstract: A data latch circuit according to embodiments described herein includes a first circuit and a second circuit. The first circuit has a first transistor with a first conductivity type and a second transistor with a second conductivity type that differs from the first conductivity type being connected in series and stores a first logical value. The second circuit has a third transistor with the first conductivity type and a fourth transistor with the second conductivity type being connected in series and stores a second logical value being an inversion of the first logical value. The data latch circuit enables one of a first voltage and a second voltage that differs from the first voltage to be applied to back gates of the first transistor and the third transistor and enables a third voltage to be applied to sources of the first transistor and the third transistor.

公开(公告)号：US20240079067A1

公开(公告)日：2024-03-07

申请号：US18176442

申请日：2023-02-28

Applicant: Kioxia Corporation

Inventor： Shouichi OZAKI ,  Kazuhiko SATOU ,  Kenro KUBOTA ,  Fumiya WATANABE ,  Atsuko SAEKI ,  Ryota TSUCHIYA ,  Harumi ABE ,  Toshifumi WATANABE

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  G11C16/32

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/32

Abstract: A semiconductor memory device includes an output pin configured for connection with a memory controller, an output circuit configured to output through the output pin a voltage signal that changes over time in accordance with one or more bits of data to be output to the memory controller, and a control circuit configured to temporarily change a drive capability of the output circuit each time a voltage signal corresponding to one bit of the data is output through the output pin.

公开(公告)号：US20230317184A1

公开(公告)日：2023-10-05

申请号：US17899971

申请日：2022-08-31

Applicant: KIOXIA CORPORATION

Inventor： Takeshi HIOKA ,  Toshifumi WATANABE

IPC: G11C16/34 ,  G11C16/10 ,  G11C7/06

CPC classification number: G11C16/3459 ,  G11C7/06 ,  G11C16/3404 ,  G11C16/102

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a word line connected to the plurality of memory cells, a plurality of bit lines connected respectively to the plurality of memory cells, a sense amplifier connected to the plurality of bit lines, and a controller configured to execute a write operation in a plurality of program loops each including a program operation and a verify operation. The sense amplifier is configured to apply a first voltage, a second voltage higher than the first voltage, a third voltage higher than the second voltage, and a fourth voltage higher than the third voltage to first, second, third, and fourth bit lines of the plurality of bit lines, respectively, while a program voltage is applied to the word line in the program operation.