公开(公告)号：US20230018613A1

公开(公告)日：2023-01-19

申请号：US17952659

申请日：2022-09-26

Applicant: Kioxia Corporation

Inventor： Junya MATSUNO ,  Kenro KUBOTA ,  Masato DOME ,  Kensuke YAMAMOTO ,  Kei SHIRAISHI ,  Kazuhiko SATOU ,  Ryo FUKUDA ,  Masaru KOYANAGI

IPC: G11C16/32 ,  G11C16/04

Abstract: A semiconductor device includes a first circuit configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level, the first voltage being higher than the second voltage. A second circuit is coupled to the first node and is configured to latch data based on a voltage of the first node; and a third circuit is coupled to the first node and is configured to output a third voltage to the first node while the first circuit is outputting the first voltage to the first node, and to output a fourth voltage to the first node while the first circuit is outputting the second voltage to the first node, the third voltage being lower than the first voltage, and the fourth voltage being higher than the second voltage.

公开(公告)号：US20220158639A1

公开(公告)日：2022-05-19

申请号：US17588702

申请日：2022-01-31

Applicant: Kioxia Corporation

Inventor： Junya MATSUNO ,  Kensuke YAMAMOTO ,  Ryo FUKUDA ,  Masaru KOYANAGI ,  Kenro KUBOTA ,  Masato DOME

IPC: H03K19/0185 ,  G11C7/10

Abstract: A semiconductor memory device includes a memory cell array and a signal propagation circuit disposed on a propagation path of a signal or a control signal. The signal propagation circuit includes a first inverted signal output circuit; a second inverted signal output circuit including an input terminal connected to an output terminal of the first inverted signal output circuit; a third inverted signal output circuit including an input terminal connected to output terminals of the first inverted signal output circuit and the second inverted signal output circuit; a fourth inverted signal output circuit including an input terminal connected to an output terminal of the third inverted signal output circuit, and further including a terminal connected to output terminals of the third inverted signal output circuit and the fourth inverted signal output circuit.

公开(公告)号：US20240312532A1

公开(公告)日：2024-09-19

申请号：US18672202

申请日：2024-05-23

Applicant: Kioxia Corporation

Inventor： Junya MATSUNO ,  Kenro KUBOTA ,  Masato DOME ,  Kensuke YAMAMOTO ,  Kei SHIRAISHI ,  Kazuhiko SATOU ,  Ryo FUKUDA ,  Masaru KOYANAGI

IPC: G11C16/32 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H10B69/00

CPC classification number: G11C16/32 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  H10B69/00

Abstract: A semiconductor memory device includes a memory cell array having a memory cell; a data signal terminal configured to receive data to be written into the memory cell from an exterior of the semiconductor memory device and to output data read from the memory cell to the exterior of the semiconductor memory, and a timing signal terminal configured to receive a timing control signal. An interface circuit includes a first comparator having a first input terminal connected to the data signal terminal, a second input terminal connected to a reference voltage, and an output terminal. A plurality of first inverters are connected in series, an input terminal of a first stage one of the first inverters being connected to the output terminal first of the first comparator. A first switch circuit has a first terminal connected to an output terminal of a final stage one of the first inverters and a second terminal; a second inverter having an input terminal connected to the second terminal of the first switch and an output terminal connected to the second terminal of the first switch; and a first latch circuit connected to the second terminal of the first switch.

公开(公告)号：US20230028971A1

公开(公告)日：2023-01-26

申请号：US17959098

申请日：2022-10-03

Applicant: Kioxia Corporation

Inventor： Masato DOME ,  Kensuke YAMAMOTO ,  Masaru KOYANAGI ,  Ryo FUKUDA ,  Junya MATSUNO ,  Kenro KUBOTA

IPC: G11C16/30 ,  G11C16/04

Abstract: According to one embodiment, a semiconductor memory device includes: first and second circuit units, a driver circuit, an input/output pad, first and second power supply pads, and first and second interconnects. The first interconnect is configured to provide coupling between the first circuit unit and the first power supply pad. The second interconnect is configured to provide coupling between the second circuit unit and the first power supply pad and have no electrical coupling to the first interconnect.

公开(公告)号：US20240097658A1

公开(公告)日：2024-03-21

申请号：US18178038

申请日：2023-03-03

Applicant: Kioxia Corporation

Inventor： Fumiya WATANABE ,  Toshifumi WATANABE ,  Kazuhiko SATOU ,  Shouichi OZAKI ,  Kenro KUBOTA ,  Atsuko SAEKI ,  Ryota TSUCHIYA ,  Harumi ABE

IPC: H03K3/011 ,  G11C7/10 ,  H03K17/14

CPC classification number: H03K3/011 ,  G11C7/1048 ,  H03K17/14 ,  G11C2207/2254 ,  H03K19/20

Abstract: A semiconductor device includes a first pad, a second pad, a first output driver provided for the first pad and configured to output a first transmission signal to the first pad, a second output driver provided for the second pad and configured to output a second transmission signal to the second pad, a register that stores first and second calibration values, a first reference resistor for the first pad and having a resistance value that is set according to the first calibration value, a second reference resistor for the second pad and having a resistance value that is set according to the second calibration value, a first setting circuit configured to calibrate a resistance value of the first output driver using the first reference resistor, and a second setting circuit configured to calibrate a resistance value of the second output driver using the second reference resistor.

公开(公告)号：US20220093185A1

公开(公告)日：2022-03-24

申请号：US17202590

申请日：2021-03-16

Applicant: Kioxia Corporation

Inventor： Masato DOME ,  Kensuke YAMAMOTO ,  Masaru KOYANAGI ,  Ryo FUKUDA ,  Junya MATSUNO ,  Kenro KUBOTA

IPC: G11C16/30 ,  G11C16/04

Abstract: According to one embodiment, a semiconductor memory device includes: first and second circuit units, a driver circuit, an input/output pad, first and second power supply pads, and first and second interconnects. The first interconnect is configured to provide coupling between the first circuit unit and the first power supply pad. The second interconnect is configured to provide coupling between the second circuit unit and the first power supply pad and have no electrical coupling to the first interconnect.

公开(公告)号：US20210226632A1

公开(公告)日：2021-07-22

申请号：US17002816

申请日：2020-08-26

Applicant: Kioxia Corporation

Inventor： Junya MATSUNO ,  Kensuke YAMAMOTO ,  Ryo FUKUDA ,  Masaru KOYANAGI ,  Kenro KUBOTA ,  Masato DOME

IPC: H03K19/0185 ,  G11C7/10

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array and a signal propagation circuit disposed on a propagation path of a signal or a control signal, wherein the signal propagation circuit includes: a first inverted signal output circuit; a second inverted signal output circuit including an input terminal connected to an output terminal of the first inverted signal output circuit; a third inverted signal output circuit including an input terminal connected to output terminals of the first inverted signal output circuit and the second inverted signal output circuit; a fourth inverted signal output circuit including an input terminal connected to an output terminal of the third inverted signal output circuit; and a fifth inverted signal output circuit including an input terminal connected to output terminals of the third inverted signal output circuit and the fourth inverted signal output circuit.

公开(公告)号：US20240079067A1

公开(公告)日：2024-03-07

申请号：US18176442

申请日：2023-02-28

Applicant: Kioxia Corporation

Inventor： Shouichi OZAKI ,  Kazuhiko SATOU ,  Kenro KUBOTA ,  Fumiya WATANABE ,  Atsuko SAEKI ,  Ryota TSUCHIYA ,  Harumi ABE ,  Toshifumi WATANABE

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  G11C16/32

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/32

Abstract: A semiconductor memory device includes an output pin configured for connection with a memory controller, an output circuit configured to output through the output pin a voltage signal that changes over time in accordance with one or more bits of data to be output to the memory controller, and a control circuit configured to temporarily change a drive capability of the output circuit each time a voltage signal corresponding to one bit of the data is output through the output pin.

公开(公告)号：US20230223938A1

公开(公告)日：2023-07-13

申请号：US18125081

申请日：2023-03-22

Applicant: Kioxia Corporation

Inventor： Junya MATSUNO ,  Kensuke YAMAMOTO ,  Ryo FUKUDA ,  Masaru KOYANAGI ,  Kenro KUBOTA ,  Masato DOME

IPC: G11C7/10

CPC classification number: G11C7/1048

Abstract: A device includes a memory cell array configured to store data; and a signal propagation circuit configured to propagate a signal between the memory cell array and a host. The signal propagation circuit includes a first inverted signal output circuit, a second inverted signal output circuit including an input terminal connected to i) an output terminal of the first inverted signal output circuit and ii) an output terminal of the second inverted signal output circuit, a third inverted signal output circuit including an input terminal connected to i) the output terminal of the first inverted signal output circuit and ii) the output terminal of the second inverted signal output circuit, and a fourth inverted signal output circuit including an input terminal connected to i) an output terminal of the third inverted signal output circuit and ii) an output terminal of the fourth inverted signal output circuit.

公开(公告)号：US20240313776A1

公开(公告)日：2024-09-19

申请号：US18594589

申请日：2024-03-04

Applicant: Kioxia Corporation

Inventor： Fumiya WATANABE ,  Kazuhiko SATOU ,  Kenro KUBOTA ,  Atsuko SAEKI ,  Ryota TSUCHIYA ,  Harumi ABE ,  Kanta NAGUMO

IPC: H03K19/00 ,  H03K19/003 ,  H03K19/0185

CPC classification number: H03K19/0005 ,  H03K19/00384 ,  H03K19/018557

Abstract: A semiconductor device includes a first circuit, a first pad, a first comparator, a second comparator, and a control circuit. The first circuit is configured to pull up a voltage of a first node, and includes a plurality of first transistors connected in parallel to the first node. The first pad is connected to the first node. The first comparator is configured to compare a voltage of the first node with a first reference voltage. The second comparator is configured to compare the voltage of the first node with a second reference voltage. The control circuit is configured to control the plurality of first transistors based on an output of the first comparator and an output of the second comparator.