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公开(公告)号：US20240055057A1
公开(公告)日：2024-02-15
申请号：US18177026
申请日：2023-03-01
Applicant: Kioxia Corporation
Inventor： Teppei HIGASHITSUJI , Toshifumi WATANABE
Abstract: A semiconductor memory includes a memory cell, a bit line electrically connected to the memory cell, a sense amplifier including a first latch circuit, a first hookup circuit, a second latch circuit, a first wiring, and a first pre-charge circuit. The sense amplifier is in a first circuit area. The first hookup circuit is in a second circuit area and configured to control connection between the bit line and the sense amplifier. The first wiring is connected between the first latch circuit and the second latch circuit. The first pre-charge circuit includes a first transistor in a third circuit area between the first circuit area and the second circuit area. The first transistor has a first end connected to the first wiring at a first position in the third circuit area and a second end connectable to a terminal supplied with one of a pre-charge voltage and a ground voltage.
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公开(公告)号：US20240046974A1
公开(公告)日：2024-02-08
申请号：US18490148
申请日：2023-10-19
Applicant: Kioxia Corporation
Inventor： Toshifumi WATANABE , Naofumi ABIKO
IPC: G11C11/4074 , G11C11/4076 , G11C11/56 , G11C11/408 , G11C11/4094
CPC classification number: G11C11/4074 , G11C11/4076 , G11C11/5642 , G11C11/4085 , G11C11/5628 , G11C11/4094 , G11C16/0483
Abstract: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.
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公开(公告)号：US20230420054A1
公开(公告)日：2023-12-28
申请号：US18243258
申请日：2023-09-07
Applicant: Kioxia Corporation
Inventor： Akio SUGAHARA , Akihiro IMAMOTO , Toshifumi WATANABE , Mami KAKOI , Kohei MASUDA , Masahiro YOSHIHARA , Naofumi ABIKO
CPC classification number: G11C16/14 , G11C16/26 , G11C16/30 , G11C16/3445
Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.
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公开(公告)号：US20210065770A1
公开(公告)日：2021-03-04
申请号：US16799402
申请日：2020-02-24
Applicant: KIOXIA CORPORATION
Inventor： Toshifumi WATANABE , Naofumi ABIKO
IPC: G11C11/4074 , G11C11/4076 , G11C11/4094 , G11C11/408 , G11C11/56
Abstract: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.
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公开(公告)号：US20230052383A1
公开(公告)日：2023-02-16
申请号：US17973549
申请日：2022-10-26
Applicant: Kioxia Corporation
Inventor： Akio SUGAHARA , Akihiro IMAMOTO , Toshifumi WATANABE , Mami KAKOI , Kohei MASUDA , Masahiro YOSHIHARA , Naofumi ABIKO
Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.
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Patent Agency Ranking
公开(公告)号：US20210225424A1
公开(公告)日：2021-07-22
申请号：US17222969
申请日：2021-04-05
Applicant: KIOXIA CORPORATION
Inventor： Toshifumi WATANABE , Naofumi ABIKO
IPC: G11C11/4074 , G11C11/4076 , G11C11/56 , G11C11/408 , G11C11/4094
Abstract: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.
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公开(公告)号：US20210202007A1
公开(公告)日：2021-07-01
申请号：US17200996
申请日：2021-03-15
Applicant: Kioxia Corporation
Inventor： Akio SUGAHARA , Akihiro IMAMOTO , Toshifumi WATANABE , Mami KAKOI , Kohei MASUDA , Masahiro YOSHIHARA , Naofumi ABIKO
Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation, and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.
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公开(公告)号：US20250095748A1
公开(公告)日：2025-03-20
申请号：US18967232
申请日：2024-12-03
Applicant: Kioxia Corporation
Inventor： Akio SUGAHARA , Akihiro IMAMOTO , Toshifumi WATANABE , Mami KAKOI , Kohei MASUDA , Masahiro YOSHIHARA , Naofumi ABIKO
Abstract: A semiconductor memory device includes plural planes each including plural blocks each including a memory cell, a voltage generator which supplies power to the plural planes, an input/output circuit which receives a command set sent from a memory controller to the semiconductor memory device, and a sequencer which executes an operation in response to the command set. Upon receiving a first command set instructing execution of a first operation, the sequencer executes the first operation. Upon receiving a command set instructing operation of a second operation during execution of the first operation, the sequencer executes the first and second operations in parallel. Upon receiving a third command set instructing execution of a third operation during execution of the first operation, the sequencer suspends the first operation, executes the third operation, and resumes the first operation upon completion of the third operation.
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公开(公告)号：US20240097658A1
公开(公告)日：2024-03-21
申请号：US18178038
申请日：2023-03-03
Applicant: Kioxia Corporation
Inventor： Fumiya WATANABE , Toshifumi WATANABE , Kazuhiko SATOU , Shouichi OZAKI , Kenro KUBOTA , Atsuko SAEKI , Ryota TSUCHIYA , Harumi ABE
CPC classification number: H03K3/011 , G11C7/1048 , H03K17/14 , G11C2207/2254 , H03K19/20
Abstract: A semiconductor device includes a first pad, a second pad, a first output driver provided for the first pad and configured to output a first transmission signal to the first pad, a second output driver provided for the second pad and configured to output a second transmission signal to the second pad, a register that stores first and second calibration values, a first reference resistor for the first pad and having a resistance value that is set according to the first calibration value, a second reference resistor for the second pad and having a resistance value that is set according to the second calibration value, a first setting circuit configured to calibrate a resistance value of the first output driver using the first reference resistor, and a second setting circuit configured to calibrate a resistance value of the second output driver using the second reference resistor.
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公开(公告)号：US20220358991A1
公开(公告)日：2022-11-10
申请号：US17873427
申请日：2022-07-26
Applicant: KIOXIA CORPORATION
Inventor： Toshifumi WATANABE , Naofumi ABIKO
IPC: G11C11/4074 , G11C11/4076 , G11C11/56 , G11C11/408 , G11C11/4094
Abstract: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.
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