公开(公告)号：US20240097658A1

公开(公告)日：2024-03-21

申请号：US18178038

申请日：2023-03-03

Applicant: Kioxia Corporation

Inventor： Fumiya WATANABE ,  Toshifumi WATANABE ,  Kazuhiko SATOU ,  Shouichi OZAKI ,  Kenro KUBOTA ,  Atsuko SAEKI ,  Ryota TSUCHIYA ,  Harumi ABE

IPC: H03K3/011 ,  G11C7/10 ,  H03K17/14

CPC classification number: H03K3/011 ,  G11C7/1048 ,  H03K17/14 ,  G11C2207/2254 ,  H03K19/20

Abstract: A semiconductor device includes a first pad, a second pad, a first output driver provided for the first pad and configured to output a first transmission signal to the first pad, a second output driver provided for the second pad and configured to output a second transmission signal to the second pad, a register that stores first and second calibration values, a first reference resistor for the first pad and having a resistance value that is set according to the first calibration value, a second reference resistor for the second pad and having a resistance value that is set according to the second calibration value, a first setting circuit configured to calibrate a resistance value of the first output driver using the first reference resistor, and a second setting circuit configured to calibrate a resistance value of the second output driver using the second reference resistor.

公开(公告)号：US20240321865A1

公开(公告)日：2024-09-26

申请号：US18590804

申请日：2024-02-28

Applicant: Kioxia Corporation

Inventor： Syunsuke SASAKI ,  Shouichi OZAKI ,  Kenichi SUGAWARA ,  Hiroaki NAKASA ,  Takeshi MIYABA ,  Maya OHSAKA ,  Shoki ITO

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L27/0266 ,  H01L27/0292 ,  H01L27/0925 ,  H01L29/0619 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a first pad to which a high voltage is to be input, a second pad to which a low voltage is to be input, a third pad to which a ground voltage is to be input, and a protection circuit provided between the first pad and the third pad. The protection circuit includes a first protection element group including a plurality of first transistors arranged in a first direction, a second protection element group including a plurality of second transistors arranged in the first direction and disposed apart from the first protection element group in a second direction orthogonal to the first direction, a guard ring provided around the first and second protection element groups, and an intermediate guard ring provided between the first protection element group and the second protection element group and connected to the third pad via a resistance element.

公开(公告)号：US20240079067A1

公开(公告)日：2024-03-07

申请号：US18176442

申请日：2023-02-28

Applicant: Kioxia Corporation

Inventor： Shouichi OZAKI ,  Kazuhiko SATOU ,  Kenro KUBOTA ,  Fumiya WATANABE ,  Atsuko SAEKI ,  Ryota TSUCHIYA ,  Harumi ABE ,  Toshifumi WATANABE

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  G11C16/32

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/32

Abstract: A semiconductor memory device includes an output pin configured for connection with a memory controller, an output circuit configured to output through the output pin a voltage signal that changes over time in accordance with one or more bits of data to be output to the memory controller, and a control circuit configured to temporarily change a drive capability of the output circuit each time a voltage signal corresponding to one bit of the data is output through the output pin.

公开(公告)号：US20240324250A1

公开(公告)日：2024-09-26

申请号：US18610282

申请日：2024-03-20

Applicant: Kioxia Corporation

Inventor： Kosuke YANAGIDAIRA ,  Yoshikazu HOSOMURA ,  Shouichi OZAKI

IPC: H10B80/00 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  H01L23/00 ,  H01L23/522 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3459 ,  H01L23/5225 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: According to one embodiment, a semiconductor memory includes a first chip including a substrate and a second chip bonded to the first chip. The second chip includes a first region including the memory cell array and the first shield line, and a second region including a second shield line. The first shield line is provided between the first chip and a memory cell array. The second shield line is provided in a same layer as the first shield line, and is not electrically coupled to the first shield line.