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134 条记录 (耗时 0.026 秒)

    Field effect transistor with reduced gate delay and method of fabricating the same
    12.
    发明授权
    Field effect transistor with reduced gate delay and method of fabricating the same 有权
    具有减小的栅极延迟的场效应晶体管及其制造方法

    公开(公告)号：US06798028B2

    公开(公告)日：2004-09-28

    申请号：US09847622

    申请日：2001-05-02

    申请人： Manfred Horstmann ,  Rolf Stephan ,  Karsten Wieczorek ,  Stephan Kruegel

    发明人： Manfred Horstmann ,  Rolf Stephan ,  Karsten Wieczorek ,  Stephan Kruegel

    IPC分类号： H01L2976

    CPC分类号： H01L21/28052 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4933

    摘要： A transistor formed on a substrate comprises a gate electrode having a lateral extension at the foot of the gate electrode that is less than the average lateral extension of the gate electrode. The increased cross-section of the gate electrode compared to the rectangular cross-sectional shape of a prior art device provides for a significantly reduced gate resistance while the effective gate length, i.e., the lateral extension of the gate electrode at its foot, may be scaled down to a size of 100 nm and beyond. Moreover, a method for forming the field effect transistor described above is disclosed.

    摘要翻译： 形成在基板上的晶体管包括栅电极，栅电极在栅极的脚处具有小于栅电极的平均横向延伸的横向延伸。 与现有技术的器件的矩形横截面形状相比，栅电极的横截面增加提供了显着降低的栅极电阻，而有效栅极长度，即栅电极在其脚处的横向延伸可以是 缩小到100nm以上的尺寸。 此外，公开了一种用于形成上述场效应晶体管的方法。

    Method of monitoring the temperature of a rapid thermal anneal process in semiconductor manufacturing and a test wafer for use in this method
    13.
    发明授权
    Method of monitoring the temperature of a rapid thermal anneal process in semiconductor manufacturing and a test wafer for use in this method 失效
    监测半导体制造中的快速热退火工艺的温度的方法和用于该方法的测试晶片

    公开(公告)号：US06436724B1

    公开(公告)日：2002-08-20

    申请号：US09808391

    申请日：2001-03-14

    申请人： Karsten Wieczorek ,  Manfred Horstmann ,  Christian Krüger

    发明人： Karsten Wieczorek ,  Manfred Horstmann ,  Christian Krüger

    IPC分类号： H01L2166

    CPC分类号： H01L22/12

    摘要： A method of monitoring the temperature of a rapid thermal annealing (RTA) process and a test wafer for use in this process are disclosed. The method includes the step of forming a distorted surface region in a crystalline semiconductor wafer and the mounting of the wafer in a process chamber for performing the RTA process in a reaction gas containing ambient. The distorted surface region of the semiconductor wafer enables higher diffusion rates of reaction gas components into the wafer surface and therefore a higher growth rate of a reaction product film. The increase of the reaction product film thickness enables an increase of the film thickness measurement accuracy and thus the accuracy in determining the RTA temperature homogeneity. In one embodiment, a distorted surface region in a crystalline silicon test wafer is produced by implanting ions at low doses into a wafer substrate up to a pre-amorphization level of the surface crystalline lattice. As a low dose of heavy ions is sufficient for producing the distorted surface region, the test wafers are produced at low costs. Additionally, a method of reworking test wafers that have been used in an RTA monitoring method is presented. By reworking the test wafers and preparing for the next RTA-monitoring the wafer costs can be efficiently reduced.

    摘要翻译： 公开了一种监测快速热退火（RTA）工艺的温度和用于该工艺的测试晶片的方法。 该方法包括在晶体半导体晶片中形成失真的表面区域以及将晶片安装在用于在含有环境的反应气体中进行RTA处理的处理室中的步骤。 半导体晶片的变形的表面区域能够使反应气体成分进入晶片表面的扩散速率更高，因此反应产物膜的生长速度更高。 反应产物膜厚度的增加能够提高膜厚测量精度，从而能够提高测定RTA温度均匀性的精度。 在一个实施例中，晶体硅测试晶片中的失真的表面区域是通过将低剂量的离子注入到晶片衬底中而产生的，直到表面晶格的非晶化阶段为止。 由于低剂量的重离子足以产生变形的表面区域，所以以低成本生产测试晶片。 另外，提出了一种在RTA监控方法中使用的重做测试晶片的方法。 通过重新测试晶片并准备下一个RTA监控，可以有效降低晶圆成本。

    Drive current adjustment for transistors by local gate engineering
    14.
    发明授权
    Drive current adjustment for transistors by local gate engineering 有权
    通过局部门工程驱动晶体管的电流调节

    公开(公告)号：US08188871B2

    公开(公告)日：2012-05-29

    申请号：US12472969

    申请日：2009-05-27

    申请人： Manfred Horstmann ,  Patrick Press ,  Karsten Wieczorek ,  Kerstin Ruttloff

    发明人： Manfred Horstmann ,  Patrick Press ,  Karsten Wieczorek ,  Kerstin Ruttloff

    IPC分类号： G08B17/00

    CPC分类号： H01L21/823462 ,  H01L21/28035 ,  H01L21/823456 ,  H01L27/11 ,  H01L29/4238 ,  H01L29/513

    摘要： In a memory cell, the drive current capabilities of the transistors may be adjusted by locally providing an increased gate dielectric thickness and/or gate length of one or more of the transistors of the memory cell. That is, the gate length and/or the gate dielectric thickness may vary along the transistor width direction, thereby providing an efficient mechanism for adjusting the effective drive current capability while at the same time allowing the usage of a simplified geometry of the active region, which may result in enhanced production yield due to enhanced process uniformity. In particular, the probability of creating short circuits caused by nickel silicide portions may be reduced.

    摘要翻译： 在存储器单元中，晶体管的驱动电流能力可以通过局部地提供存储单元的一个或多个晶体管的增加的栅介质厚度和/或栅极长度来调节。 也就是说，栅极长度和/或栅极电介质厚度可以沿晶体管宽度方向变化，从而提供用于调节有效驱动电流能力的有效机构，同时允许使用有源区域的简化几何形状， 这可能由于增加的工艺均匀性而导致产量提高。 特别地，可能减少由硅化镍部分引起的产生短路的可能性。

    Method of forming a metal silicide
    17.
    发明授权
    Method of forming a metal silicide 失效
    形成金属硅化物的方法

    公开(公告)号：US07067410B2

    公开(公告)日：2006-06-27

    申请号：US10835182

    申请日：2004-04-29

    申请人： Karsten Wieczorek ,  Thorsten Kammler ,  Manfred Horstmann

    发明人： Karsten Wieczorek ,  Thorsten Kammler ,  Manfred Horstmann

    IPC分类号： H01L21/3205

    CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/28518 ,  H01L29/665

    摘要： The present invention provides a technique for forming a metal silicide, such as a cobalt disilicide, even at extremely scaled device dimensions without unduly degrading the film integrity of the metal silicide. To this end, an ion implantation may be performed, advantageously with silicon, prior to a final anneal cycle, thereby correspondingly modifying the grain structure of the precursor of the metal silicide.

    摘要翻译： 本发明提供了一种用于形成诸如二硅化钴之类的金属硅化物的技术，即使在极度缩放的器件尺寸下，也不会不利地降低金属硅化物的膜完整性。 为此，可以在最终退火循环之前有利地利用硅进行离子注入，从而相应地改变金属硅化物的前体的晶粒结构。

    Semiconductor device having a retrograde dopant profile in a channel region and method for fabricating the same
    18.
    发明授权
    Semiconductor device having a retrograde dopant profile in a channel region and method for fabricating the same 有权
    在沟道区域具有逆向掺杂剂分布的半导体器件及其制造方法

    公开(公告)号：US06881641B2

    公开(公告)日：2005-04-19

    申请号：US10282980

    申请日：2002-10-29

    申请人： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

    发明人： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L21/331

    CPC分类号： H01L21/823807 ,  H01L29/1054 ,  H01L29/6659

    摘要： An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in the channel layer is significantly reduced compared to a conventional device to thereby provide a retrograde dopant profile in a channel region of a field effect transistor. Additionally, a barrier diffusion layer may be provided between the well structure and the channel layer to reduce up-diffusion during any heat treatments carried out after the formation of the channel layer. The final dopant profile in the channel region may be adjusted by the thickness of the channel layer, the thickness and the composition of the diffusion barrier layer and any additional implantation steps to introduce dopant atoms in the channel layer.

    摘要翻译： 在离子注入步骤之后在阱结构上提供外延生长的沟道层，并且进行热处理步骤以在阱结构中建立所需的掺杂剂分布。 根据需要，沟道层可以是未掺杂的或稍微掺杂的，使得与常规器件相比，沟道层中最终获得的掺杂剂浓度显着降低，从而在场效应晶体管的沟道区域中提供逆向掺杂物分布。 此外，可以在阱结构和沟道层之间提供阻挡扩散层，以在形成沟道层之后进行的任何热处理期间减小向上扩散。 可以通过沟道层的厚度，扩散阻挡层的厚度和组成以及在沟道层中引入掺杂剂原子的任何额外的注入步骤来调整沟道区中的最终掺杂物分布。