公开(公告)号：US20130346680A1

公开(公告)日：2013-12-26

申请号：US13530169

申请日：2012-06-22

申请人： Ross S. Scouller ,  Frank K. Baker, JR. ,  Ronald J. Syzdek

发明人： Ross S. Scouller ,  Frank K. Baker, JR. ,  Ronald J. Syzdek

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7207

摘要： A memory system comprises a memory controller, an address RAM coupled to the memory controller, and a non-volatile memory coupled to the memory controller. The non-volatile memory has an address portion and a data portion. The address portion of the non-volatile memory provides data portion addresses and data portion addresses of valid data to the memory controller. The memory controller loads the data portion addresses and stores them in the address RAM at locations defined by the data portion addresses of valid data into the address RAM. The memory controller uses the data portion addresses, and locations of data blocks within the address RAM, to locate the data blocks within the data portion of non-volatile memory. The memory controller uses the data portion addresses, and locations of the data block addresses within the address RAM, to locate data blocks within the data portion of non-volatile memory

摘要翻译： 存储器系统包括存储器控制器，耦合到存储器控制器的地址RAM以及耦合到存储器控制器的非易失性存储器。 非易失性存储器具有地址部分和数据部分。 非易失性存储器的地址部分向存储器控制器提供有效数据的数据部分地址和数据部分地址。 存储器控制器加载数据部分地址并将它们存储在地址RAM中，在由有效数据的数据部分地址定义的地址到地址RAM中。 存储器控制器使用数据部分地址和地址RAM内的数据块的位置来定位非易失性存储器的数据部分内的数据块。 存储器控制器使用数据部分地址和地址RAM内的数据块地址的位置来定位非易失性存储器的数据部分内的数据块

公开(公告)号：US07742340B2

公开(公告)日：2010-06-22

申请号：US12048683

申请日：2008-03-14

申请人： Fuchen Mu ,  Marco A. Cabassi ,  Ronald J. Syzdek

发明人： Fuchen Mu ,  Marco A. Cabassi ,  Ronald J. Syzdek

IPC分类号： G11C16/06

CPC分类号： G11C16/28 ,  G11C7/14 ,  G11C11/5642

摘要： A set of reference cells is used for sensing the data values stored at bit cells of a memory device. In response to an event, the reference cell providing the highest output of the set is selected as the reference cell to be used for subsequent memory access operations. The remaining reference cells are disabled so that they can recover back to or near their original non-degraded states. At each successive event, the set of reference cells can be reassessed to identify the reference cell that provides the highest output at that time and the memory device can be reconfigured to utilize the reference cell so identified. By utilizing the reference cell having the highest output to provide the read reference and disabling the remaining reference cells, the likelihood of the read reference falling below a minimum threshold can be reduced.

摘要翻译： 一组参考单元用于感测存储在存储器件的位单元中的数据值。 响应于事件，提供集合的最高输出的参考单元被选择为用于后续存储器存取操作的参考单元。 剩余的参考单元被禁用，使得它们可以恢复到其原始非退化状态或其附近。 在每个连续事件中，可以重新评估参考单元集合以识别在该时间提供最高输出的参考单元，并且可重新配置存储器件以利用如此识别的参考单元。 通过利用具有最高输出的参考单元来提供读取参考并禁用剩余的参考单元，可以减少低于最小阈值的读取参考的可能性。

公开(公告)号：US20140211559A1

公开(公告)日：2014-07-31

申请号：US13751548

申请日：2013-01-28

申请人： Cheong M. Hong ,  Ronald J. Syzdek ,  Brian A. Winstead

发明人： Cheong M. Hong ,  Ronald J. Syzdek ,  Brian A. Winstead

IPC分类号： G11C11/40

CPC分类号： G11C11/40 ,  G11C16/12

摘要： A method of programming a split gate memory applies voltages differently to the terminals of the selected cells and the deselected cells. For cells being programming by being coupled to a selected row and a selected column, coupling the control gate to a first voltage, coupling the select gate to a second voltage, programming is achieved by coupling the drain terminal to a current sink that causes the split gate memory cell to be conductive, and coupling the source terminal to a third voltage. For cells not being programmed by not being coupled to a selected row, non-programming is maintained by coupling the control gate to the first voltage, coupling the select gate to a fourth voltage which is greater than a voltage applied to the select gate during a read in which the split gate memory cells are deselected but sufficiently low to prevent programming.

摘要翻译： 编程分离栅极存储器的方法对所选择的单元和未选择的单元的端子不同地施加电压。 对于通过耦合到选定的列和选定的列进行编程的单元，将控制栅极耦合到第一电压，将选择栅极耦合到第二电压，通过将漏极端子耦合到导致分裂的电流阱来实现编程 栅极存储单元导通，并将源极端子耦合到第三电压。 对于不是通过不耦合到所选择的行来编程的单元，通过将控制栅极耦合到第一电压来维持非编程，将选择栅极耦合到第四电压，该第四电压大于施加到选择栅极的电压 读取分离栅极存储单元被取消选择但足够低以防止编程。

公开(公告)号：US20090231925A1

公开(公告)日：2009-09-17

申请号：US12048683

申请日：2008-03-14

申请人： Fuchen Mu ,  Marco A. Cabassi ,  Ronald J. Syzdek

发明人： Fuchen Mu ,  Marco A. Cabassi ,  Ronald J. Syzdek

IPC分类号： G11C16/06 ,  G11C16/26

CPC分类号： G11C16/28 ,  G11C7/14 ,  G11C11/5642

摘要： A set of reference cells is used for sensing the data values stored at bit cells of a memory device. In response to an event, the reference cell providing the highest output of the set is selected as the reference cell to be used for subsequent memory access operations. The remaining reference cells are disabled so that they can recover back to or near their original non-degraded states. At each successive event, the set of reference cells can be reassessed to identify the reference cell that provides the highest output at that time and the memory device can be reconfigured to utilize the reference cell so identified. By utilizing the reference cell having the highest output to provide the read reference and disabling the remaining reference cells, the likelihood of the read reference falling below a minimum threshold can be reduced.

摘要翻译： 一组参考单元用于感测存储在存储器件的位单元中的数据值。 响应于事件，提供集合的最高输出的参考单元被选择为用于后续存储器存取操作的参考单元。 剩余的参考单元被禁用，使得它们可以恢复到其原始非退化状态或其附近。 在每个连续事件中，可以重新评估参考单元集合以识别在该时间提供最高输出的参考单元，并且可重新配置存储器件以利用如此识别的参考单元。 通过利用具有最高输出的参考单元来提供读取参考并禁用剩余的参考单元，可以减少低于最小阈值的读取参考的可能性。

公开(公告)号：US20080117685A1

公开(公告)日：2008-05-22

申请号：US11560554

申请日：2006-11-16

申请人： Ronald J. Syzdek ,  David W. Chrudimsky ,  Xiaojie He

发明人： Ronald J. Syzdek ,  David W. Chrudimsky ,  Xiaojie He

IPC分类号： G11C16/28

CPC分类号： G11C16/28

摘要： A read reference level of a plurality of read reference is determined for a set of bit cells of a non-volatile memory array. An indicator of the read reference level is stored in a non-volatile storage location associated with the set of bit cells. The indicator of the read reference level is accessed in response to a read access operation to the set of bit cells and a value stored at a memory location of the set of bit cells is sensed based on the indicator of the read reference level, whereby the memory location of the set of bit cells is associated with the read access operation.

摘要翻译： 为非易失性存储器阵列的一组位单元确定多个读取参考的读取参考电平。 读取参考电平的指示符存储在与该位单元组相关联的非易失性存储单元中。 读取参考电平的指示符是响应于对该组单元的读取访问操作而被访问的，并且基于所读取的参考电平的指示符来感测存储在该位组单元的存储单元处的值， 该位单元组的存储器位置与读访问操作相关联。

公开(公告)号：US5668769A

公开(公告)日：1997-09-16

申请号：US560229

申请日：1995-11-21

申请人： Tim M. Coffman ,  Ronald J. Syzdek ,  Timothy J. Coots ,  Phat C. Truong ,  Sung-Wei Lin

发明人： Tim M. Coffman ,  Ronald J. Syzdek ,  Timothy J. Coots ,  Phat C. Truong ,  Sung-Wei Lin

IPC分类号： G11C11/41 ,  G11C7/22 ,  G11C11/409 ,  G11C7/00

CPC分类号： G11C7/22

摘要： The method of this invention prevents transient currents at high-frequency disable cycles and disables DC current paths after a minimum delay time, thereby reducing power dissipation. This invention includes a delay circuit functioning to prevent disablement of DC paths where chip-disable times occur at intervals below a minimum duration. The result is a decrease in the number of undesired voltage drops on internal power buses due to transient currents. The method detects external chip-disable pulses that occur before a minimum time duration, then prevents those pulses from powering down internal direct-current paths. At the same time, the output driver high impedance functionality of the chip-disable signal is preserved.

摘要翻译： 本发明的方法防止在高频禁用周期的瞬态电流，并且在最小延迟时间之后禁用直流电流路径，从而降低功耗。 本发明包括延迟电路，其功能是防止在低于最小持续时间的间隔下发生芯片禁止时间的DC路径的禁用。 结果是由于瞬态电流，内部电力总线上的不期望的电压降的数量减少。 该方法检测在最小持续时间之前发生的外部芯片禁止脉冲，然后防止这些脉冲掉电内部直流路径。 同时，保持了芯片禁止信号的输出驱动器高阻抗功能。

公开(公告)号：US07865797B2

公开(公告)日：2011-01-04

申请号：US11560533

申请日：2006-11-16

申请人： Richard K. Eguchi ,  Ronald J. Syzdek

发明人： Richard K. Eguchi ,  Ronald J. Syzdek

IPC分类号： H03M13/00

CPC分类号： G06F11/1008 ,  G11C16/28

摘要： A first value from a set of bit cells of a sector of a non-volatile memory device is sensed based on a first read reference. A second value from the set of bit cells is sensed based on a second read reference different than the first read reference. A third read reference for a first subsequent access to the sector of the non-volatile memory device is determined based on at least one of the first read reference and the second read reference in response to determining a first error code condition associated with the first value and a second error code condition associated with the second value represent different error code conditions.

摘要翻译： 基于第一读取参考来感测来自非易失性存储器件的扇区的一组位单元的第一值。 基于与第一读取参考不同的第二读取参考来感测来自位单元组的第二值。 响应于确定与第一值相关联的第一错误代码条件，基于第一读取参考和第二读取参考中的至少一个来确定用于对非易失性存储器设备的扇区的第一后续访问的第三读取参考 并且与第二值相关联的第二错误代码条件表示不同的错误代码条件。

公开(公告)号：US07843730B2

公开(公告)日：2010-11-30

申请号：US12015247

申请日：2008-01-16

申请人： Ronald J. Syzdek

发明人： Ronald J. Syzdek

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C5/06

CPC分类号： G11C16/0433 ,  G11C16/10

摘要： A method including performing a program/erase cycle on a first non-volatile memory (NVM) bit of an integrated circuit using a first fluence, wherein the first NVM bit has a first transconductance is provided. The method further includes performing a program/erase cycle on a second NVM bit of the integrated circuit using a second fluence, wherein the second NVM bit has a second transconductance, and wherein the first transconductance is greater than the second transconductance and the second fluence is greater than the first fluence.

摘要翻译： 一种方法，包括使用第一能量密度对集成电路的第一非易失性存储器（NVM）位执行编程/擦除周期，其中提供第一NVM位具有第一跨导。 该方法还包括使用第二能量密度对集成电路的第二NVM位执行编程/擦除周期，其中第二NVM位具有第二跨导，并且其中第一跨导大于第二跨导，而第二能量密度是 大于第一流利。

公开(公告)号：US07668018B2

公开(公告)日：2010-02-23

申请号：US11695722

申请日：2007-04-03

申请人： Ronald J. Syzdek ,  Gowrishankar L. Chindalore ,  Thomas Jew

发明人： Ronald J. Syzdek ,  Gowrishankar L. Chindalore ,  Thomas Jew

IPC分类号： G11C16/04

CPC分类号： G11C16/349

摘要： An electronic device can include a first memory cell and a second memory cell. The first memory cell can include a first source, and a second memory cell can include a second source. The first memory cell and the second memory cell can lie within a same sector of a memory array. In one embodiment, erasing the electronic device can include erasing the first memory cell while inhibiting the erase of the second memory cell. A third memory cell can have a third source and lie within another sector. In another embodiment, inhibiting the erase of the first memory cell can include placing the first source and the third source at a same potential. In a particular embodiment, the first source can be electrically insulated from the second source.

摘要翻译： 电子设备可以包括第一存储器单元和第二存储单元。 第一存储单元可以包括第一源，而第二存储单元可以包括第二源。 第一存储器单元和第二存储器单元可以位于存储器阵列的相同扇区内。 在一个实施例中，擦除电子设备可以包括在禁止第二存储器单元的擦除的同时擦除第一存储器单元。 第三存储器单元可具有第三源并位于另一扇区内。 在另一个实施例中，禁止第一存储器单元的擦除可以包括将第一源和第三源放置在相同的电位。 在特定实施例中，第一源可以与第二源电绝缘。

公开(公告)号：US07564716B2

公开(公告)日：2009-07-21

申请号：US11560554

申请日：2006-11-16

申请人： Ronald J. Syzdek ,  David W. Chrudimsky ,  Xiaojie He

发明人： Ronald J. Syzdek ,  David W. Chrudimsky ,  Xiaojie He

IPC分类号： G11C11/34

CPC分类号： G11C16/28

摘要： A read reference level of a plurality of read reference is determined for a set of bit cells of a non-volatile memory array. An indicator of the read reference level is stored in a non-volatile storage location associated with the set of bit cells. The indicator of the read reference level is accessed in response to a read access operation to the set of bit cells and a value stored at a memory location of the set of bit cells is sensed based on the indicator of the read reference level, whereby the memory location of the set of bit cells is associated with the read access operation.

摘要翻译： 为非易失性存储器阵列的一组位单元确定多个读取参考的读取参考电平。 读取参考电平的指示符存储在与该位单元组相关联的非易失性存储单元中。 读取参考电平的指示符是响应于对该组单元的读取访问操作而被访问的，并且基于所读取的参考电平的指示符来感测存储在该位组单元的存储单元处的值， 该位单元组的存储器位置与读访问操作相关联。