公开(公告)号：US20140211559A1

公开(公告)日：2014-07-31

申请号：US13751548

申请日：2013-01-28

申请人： Cheong M. Hong ,  Ronald J. Syzdek ,  Brian A. Winstead

发明人： Cheong M. Hong ,  Ronald J. Syzdek ,  Brian A. Winstead

IPC分类号： G11C11/40

CPC分类号： G11C11/40 ,  G11C16/12

摘要： A method of programming a split gate memory applies voltages differently to the terminals of the selected cells and the deselected cells. For cells being programming by being coupled to a selected row and a selected column, coupling the control gate to a first voltage, coupling the select gate to a second voltage, programming is achieved by coupling the drain terminal to a current sink that causes the split gate memory cell to be conductive, and coupling the source terminal to a third voltage. For cells not being programmed by not being coupled to a selected row, non-programming is maintained by coupling the control gate to the first voltage, coupling the select gate to a fourth voltage which is greater than a voltage applied to the select gate during a read in which the split gate memory cells are deselected but sufficiently low to prevent programming.

摘要翻译： 编程分离栅极存储器的方法对所选择的单元和未选择的单元的端子不同地施加电压。 对于通过耦合到选定的列和选定的列进行编程的单元，将控制栅极耦合到第一电压，将选择栅极耦合到第二电压，通过将漏极端子耦合到导致分裂的电流阱来实现编程 栅极存储单元导通，并将源极端子耦合到第三电压。 对于不是通过不耦合到所选择的行来编程的单元，通过将控制栅极耦合到第一电压来维持非编程，将选择栅极耦合到第四电压，该第四电压大于施加到选择栅极的电压 读取分离栅极存储单元被取消选择但足够低以防止编程。

公开(公告)号：US08885403B2

公开(公告)日：2014-11-11

申请号：US13751548

申请日：2013-01-28

申请人： Cheong M. Hong ,  Ronald J. Syzdek ,  Brian A. Winstead

发明人： Cheong M. Hong ,  Ronald J. Syzdek ,  Brian A. Winstead

IPC分类号： G11C11/34 ,  G11C11/40

CPC分类号： G11C11/40 ,  G11C16/12

摘要： A method of programming a split gate memory applies voltages differently to the terminals of the selected cells and the deselected cells. For cells being programming by being coupled to a selected row and a selected column, coupling the control gate to a first voltage, coupling the select gate to a second voltage, programming is achieved by coupling the drain terminal to a current sink that causes the split gate memory cell to be conductive, and coupling the source terminal to a third voltage. For cells not being programmed by not being coupled to a selected row, non-programming is maintained by coupling the control gate to the first voltage, coupling the select gate to a fourth voltage which is greater than a voltage applied to the select gate during a read in which the split gate memory cells are deselected but sufficiently low to prevent programming.

摘要翻译： 编程分离栅极存储器的方法对所选择的单元和未选择的单元的端子不同地施加电压。 对于通过耦合到选定的列和选定的列进行编程的单元，将控制栅极耦合到第一电压，将选择栅极耦合到第二电压，通过将漏极端子耦合到导致分裂的电流阱来实现编程 栅极存储单元导通，并将源极端子耦合到第三电压。 对于不是通过不耦合到所选择的行来编程的单元，通过将控制栅极耦合到第一电压来维持非编程，将选择栅极耦合到第四电压，该第四电压大于施加到选择栅极的电压 读取分离栅极存储单元被取消选择但足够低以防止编程。

公开(公告)号：US07957190B2

公开(公告)日：2011-06-07

申请号：US12130197

申请日：2008-05-30

申请人： Cheong M. Hong ,  Sung-Taeg Kang ,  Brian A. Winstead

发明人： Cheong M. Hong ,  Sung-Taeg Kang ,  Brian A. Winstead

IPC分类号： G11C16/04

CPC分类号： G11C16/0425

摘要： A memory comprising a plurality of P-channel split-gate memory cells are organized in rows and columns. Each of the plurality of P-channel split-gate memory cells comprises a select gate, a control gate, a source region, a drain region, a channel region, and a charge storage layer comprising nanocrystals. Programming a memory cell of the plurality of P-channel split-gate memory cells comprises injecting electrons from a channel region of the memory cell to the charge storage layer. Erasing the memory cell comprises injecting holes from the channel region to the charge storage region.

摘要翻译： 包括多个P沟道分裂门存储器单元的存储器以行和列组织。 多个P沟道分离栅极存储单元中的每一个包括选择栅极，控制栅极，源极区域，漏极区域，沟道区域和包含纳米晶体的电荷存储层。 编程多个P沟道分离栅极存储单元的存储单元包括将电子从存储单元的沟道区域注入电荷存储层。 擦除存储单元包括从通道区域向电荷存储区域注入空穴。

公开(公告)号：US20090296491A1

公开(公告)日：2009-12-03

申请号：US12130197

申请日：2008-05-30

申请人： Cheong M. Hong ,  Sung-Taeg Kang ,  Brian A. Winstead

发明人： Cheong M. Hong ,  Sung-Taeg Kang ,  Brian A. Winstead

IPC分类号： G11C16/06

CPC分类号： G11C16/0425

摘要： A memory comprising a plurality of P-channel split-gate memory cells are organized in rows and columns. Each of the plurality of P-channel split-gate memory cells comprises a select gate, a control gate, a source region, a drain region, a channel region, and a charge storage layer comprising nanocrystals. Programming a memory cell of the plurality of P-channel split-gate memory cells comprises injecting electrons from a channel region of the memory cell to the charge storage layer. Erasing the memory cell comprises injecting holes from the channel region to the charge storage region.

摘要翻译： 包括多个P沟道分裂门存储器单元的存储器以行和列组织。 多个P沟道分离栅极存储单元中的每一个包括选择栅极，控制栅极，源极区域，漏极区域，沟道区域和包含纳米晶体的电荷存储层。 编程多个P沟道分离栅极存储单元的存储单元包括将电子从存储单元的沟道区域注入电荷存储层。 擦除存储单元包括从通道区域向电荷存储区域注入空穴。

公开(公告)号：US20100244121A1

公开(公告)日：2010-09-30

申请号：US12414763

申请日：2009-03-31

申请人： Konstantin V. Loiko ,  Cheong M. Hong ,  Sung-Taeg Kang ,  Taras A. Kirichenko ,  Brian A. Winstead

发明人： Konstantin V. Loiko ,  Cheong M. Hong ,  Sung-Taeg Kang ,  Taras A. Kirichenko ,  Brian A. Winstead

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/42328 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/7881

摘要： A method of making a semiconductor device on a semiconductor layer includes forming a gate dielectric and a first layer of gate material over the gate dielectric. The first layer is etched to remove a portion of the first layer of gate material over a first portion of the semiconductor layer and to leave a select gate portion. A storage layer is formed over the select gate portion and over the first portion of the semiconductor layer. A second layer of gate material is formed over the storage layer. The second layer of gate material is etched to remove a first portion of the second layer of gate material over a first portion of the select gate portion. A portion of the first portion of the select gate is etched out to leave an L-shaped select structure. The result is a memory cell with an L-shaped select gate.

摘要翻译： 在半导体层上制造半导体器件的方法包括在栅极电介质上形成栅极电介质和栅极材料的第一层。 第一层被蚀刻以在半导体层的第一部分上移除第一层栅极材料的一部分并留下选择栅极部分。 存储层形成在选择栅极部分上方和半导体层的第一部分之上。 在存储层上形成第二层栅极材料层。 第二层栅极材料被蚀刻以在选择栅极部分的第一部分上去除第二层栅极材料的第一部分。 选择栅极的第一部分的一部分被蚀刻以留下L形选择结构。 结果是具有L形选择栅极的存储单元。

公开(公告)号：US07985649B1

公开(公告)日：2011-07-26

申请号：US12683972

申请日：2010-01-07

申请人： Brian A. Winstead ,  Cheong M. Hong ,  Sung-Taeg Kang ,  Konstantin V. Loiko ,  Spencer E. Williams

发明人： Brian A. Winstead ,  Cheong M. Hong ,  Sung-Taeg Kang ,  Konstantin V. Loiko ,  Spencer E. Williams

IPC分类号： H01L21/336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/7881

摘要： A method of making a semiconductor device on a semiconductor layer is provided. The method includes: forming a select gate dielectric layer over the semiconductor layer; forming a select gate layer over the select gate dielectric layer; and forming a sidewall of the select gate layer by removing at least a portion of the select gate layer. The method further includes growing a sacrificial layer on at least a portion of the sidewall of the select gate layer and under at least a portion of the select gate layer and removing the sacrificial layer to expose a surface of the at least portion of the sidewall of the select gate layer and a surface of the semiconductor layer under the select gate layer. The method further includes forming a control gate dielectric layer, a charge storage layer, and a control gate layer.

摘要翻译： 提供了在半导体层上制造半导体器件的方法。 该方法包括：在半导体层上形成选择栅介质层; 在所述选择栅介质层上形成选择栅层; 以及通过去除所述选择栅极层的至少一部分来形成所述选择栅极层的侧壁。 该方法还包括在选择栅极层的侧壁的至少一部分上并在选择栅极层的至少一部分下方生长牺牲层，并且去除牺牲层以暴露侧壁的至少部分的表面 选择栅极层和选择栅极层下方的半导体层的表面。 该方法还包括形成控制栅介质层，电荷存储层和控制栅层。

公开(公告)号：US20110165749A1

公开(公告)日：2011-07-07

申请号：US12683972

申请日：2010-01-07

申请人： Brian A. Winstead ,  Cheong M. Hong ,  Sung-Taeg Kang ,  Konstantin V. Loiko ,  Spencer E. Williams

发明人： Brian A. Winstead ,  Cheong M. Hong ,  Sung-Taeg Kang ,  Konstantin V. Loiko ,  Spencer E. Williams

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/7881

摘要： A method of making a semiconductor device on a semiconductor layer is provided. The method includes: forming a select gate dielectric layer over the semiconductor layer; forming a select gate layer over the select gate dielectric layer; and forming a sidewall of the select gate layer by removing at least a portion of the select gate layer. The method further includes growing a sacrificial layer on at least a portion of the sidewall of the select gate layer and under at least a portion of the select gate layer and removing the sacrificial layer to expose a surface of the at least portion of the sidewall of the select gate layer and a surface of the semiconductor layer under the select gate layer. The method further includes forming a control gate dielectric layer, a charge storage layer, and a control gate layer.

摘要翻译： 提供了在半导体层上制造半导体器件的方法。 该方法包括：在半导体层上形成选择栅介质层; 在所述选择栅介质层上形成选择栅层; 以及通过去除所述选择栅极层的至少一部分来形成所述选择栅极层的侧壁。 该方法还包括在选择栅极层的侧壁的至少一部分上并在选择栅极层的至少一部分下方生长牺牲层，并且去除牺牲层以暴露侧壁的至少部分的表面 选择栅极层和选择栅极层下方的半导体层的表面。 该方法还包括形成控制栅介质层，电荷存储层和控制栅层。

公开(公告)号：US08643123B2

公开(公告)日：2014-02-04

申请号：US13085533

申请日：2011-04-13

申请人： Cheong M. Hong ,  Brian A. Winstead

发明人： Cheong M. Hong ,  Brian A. Winstead

IPC分类号： H01L21/02

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L29/66825

摘要： A semiconductor device comprises a semiconductor substrate and a select gate structure over a first portion of the semiconductor substrate. The select gate structure comprises a sidewall forming a corner with a second portion of the semiconductor substrate and a charge storage stack over an area comprising the second portion of the semiconductor substrate, the sidewall, and the corner. A corner portion of a top surface of the charge storage stack is non-conformal with the corner, and the corner portion of the top surface of the charge storage stack has a radius of curvature measuring approximately one-third of a thickness of the charge storage stack over the second portion of the substrate or greater. A control gate layer is formed over the charge storage stack. A portion of the control gate layer conforms to the corner portion of the top surface of the charge storage stack.

摘要翻译： 半导体器件包括在半导体衬底的第一部分上的半导体衬底和选择栅极结构。 选择栅极结构包括形成具有半导体衬底的第二部分的角部的侧壁和在包括半导体衬底的第二部分，侧壁和角部的区域上的电荷存储堆叠。 电荷存储堆的顶表面的角部与拐角不一致，并且电荷存储堆的顶表面的角部具有测量电荷存储的厚度的约三分之一的曲率半径 堆叠在衬底的第二部分上或更大。 在电荷存储堆上形成控制栅层。 控制栅极层的一部分符合电荷存储堆的顶表面的角部。

公开(公告)号：US07821055B2

公开(公告)日：2010-10-26

申请号：US12414763

申请日：2009-03-31

申请人： Konstantin V. Loiko ,  Cheong M. Hong ,  Sung-Taeg Kang ,  Taras A. Kirichenko ,  Brian A. Winstead

发明人： Konstantin V. Loiko ,  Cheong M. Hong ,  Sung-Taeg Kang ,  Taras A. Kirichenko ,  Brian A. Winstead

IPC分类号： H01L29/788 ,  H01L29/792

CPC分类号： H01L29/42328 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/7881

摘要： A method of making a semiconductor device on a semiconductor layer includes forming a gate dielectric and a first layer of gate material over the gate dielectric. The first layer is etched to remove a portion of the first layer of gate material over a first portion of the semiconductor layer and to leave a select gate portion. A storage layer is formed over the select gate portion and over the first portion of the semiconductor layer. A second layer of gate material is formed over the storage layer. The second layer of gate material is etched to remove a first portion of the second layer of gate material over a first portion of the select gate portion. A portion of the first portion of the select gate is etched out to leave an L-shaped select structure. The result is a memory cell with an L-shaped select gate.

摘要翻译： 在半导体层上制造半导体器件的方法包括在栅极电介质上形成栅极电介质和栅极材料的第一层。 第一层被蚀刻以在半导体层的第一部分上移除第一层栅极材料的一部分并留下选择栅极部分。 存储层形成在选择栅极部分上方和半导体层的第一部分之上。 在存储层上形成第二层栅极材料层。 第二层栅极材料被蚀刻以在选择栅极部分的第一部分上移除第二层栅极材料的第一部分。 选择栅极的第一部分的一部分被蚀刻以留下L形选择结构。 结果是具有L形选择栅极的存储单元。

公开(公告)号：US09257445B2

公开(公告)日：2016-02-09

申请号：US14291224

申请日：2014-05-30

申请人： Konstantin V. Loiko ,  Brian A. Winstead

发明人： Konstantin V. Loiko ,  Brian A. Winstead

IPC分类号： H01L29/49 ,  H01L27/115 ,  H01L21/285 ,  H01L29/423 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28525 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792

摘要： Semiconductor structures and methods for making semiconductor structures include a split gate non-volatile memory (NVM) cell in an NVM region. A charge storage layer, a first conductive layer, and a capping layer are formed over the substrate, which are patterned to form a control gate stack in the NVM region of the substrate. A high-k dielectric layer, a metal layer, and a second conductive layer are formed over the substrate. The second conductive layer and the metal layer are patterned to form remaining portions of the second conductive layer and the metal layer over and adjacent to a first side of the control gate stack. The remaining portion of the second conductive layer is removed to form a select gate stack, which includes the remaining portion of the metal layer. A stressor layer is formed over the substrate.

摘要翻译： 用于制造半导体结构的半导体结构和方法包括NVM区域中的分裂门非易失性存储器（NVM）单元。 电荷存储层，第一导电层和覆盖层形成在衬底上，其被图案化以在衬底的NVM区域中形成控制栅极堆叠。 在基板上形成高k电介质层，金属层和第二导电层。 图案化第二导电层和金属层，以在控制栅极堆叠的第一侧上并与之相邻地形成第二导电层和金属层的剩余部分。 去除第二导电层的剩余部分以形成包括金属层的剩余部分的选择栅叠层。 在衬底上形成应力层。